AT25DL081-SSHN-B Adesto Technologies, AT25DL081-SSHN-B Datasheet
AT25DL081-SSHN-B
Specifications of AT25DL081-SSHN-B
Related parts for AT25DL081-SSHN-B
AT25DL081-SSHN-B Summary of contents
Page 1
... Complies with full industrial temperature range Industry standard green (Pb/halide-free/RoHS-compliant) package options 8-lead SOIC (0.150” wide) 8-pad Ultra-thin DFN ( 0.6mm) 8-ball dBGA (WLCSP) AT25DL081 with Dual-I/O Support DATASHEET 8732E–DFLASH–1/2013 ...
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... Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25DL081, with its erase granularity as small as 4KB, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices. ...
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... The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However recommended that the WP pin also be externally connected to VCC whenever possible. Asserted State Low — — — for more details on Low AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 Type Input Input Input/Output Input/Output Input 3 ...
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... SO (SOI) HOLD SCK 3 6 GND SI (SIO Asserted State Type Low Input — Power — Power Figure 2-3. 8-ball dBGA VCC CS C HOLD SO (SOI) D SCK (SIO) GND F Top View through back of Die AT25DL081 [DATASHEET] 4 8732E–DFLASH–1/2013 ...
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... SCK Interface Control SI (SIO) and Logic SO (SOI) WP HOLD Note: SIO and SOI pin naming convention is used for Dual-I/O commands. Control and Protection Logic Y-Decoder X-Decoder AT25DL081 [DATASHEET] I/O Buffers and Latches SRAM Data Buffer Y-Gating Flash Memory Array 5 8732E–DFLASH–1/2013 ...
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... Memory Array To provide the greatest flexibility, the AT25DL081 memory array can be erased in four levels of granularity, including a full Chip Erase. In addition, the array has been divided into physical sectors of uniform size, which can be individually protected from program and erase operations. The size of the physical sectors is optimized for both code and data storage applications, allowing both code and data segments to reside in their own isolated regions ...
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... Device Operation The AT25DL081 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with the AT25DL081 via the SPI bus, which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO). ...
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... Up to 100MHz 31h 0011 0001 Up to 100MHz F0h 1111 0000 Up to 100MHz 9Fh 1001 1111 Up to 85MHz B9h 1011 1001 Up to 100MHz ABh 1010 1011 Up to 100MHz AT25DL081 [DATASHEET] Address Dummy Data Bytes Bytes Bytes ...
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... Don't Care MSB Don't Care MSB Data Byte MSB AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 MSB 9 ...
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... Address Bits A23- MSB Data Byte MSB Data Byte MSB MSB MSB AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 10 ...
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... Output Output Don't Care Data Byte 1 Data Byte MSB MSB MSB AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 . To RDDO ...
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... If a programming error arises, it will be indicated by the EPE bit in the Status Register. “Write Enable” on page 21) to set the Write Enable Latch (WEL) bit of the 29), then the Byte/Page Program command will not be executed and the AT25DL081 [DATASHEET] “Protect Sector” on page 23 ...
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... D D MSB MSB Address Bits A23-A0 Data In Byte MSB MSB Data In Byte MSB AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 13 ...
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... If a programming error arises, it will be indicated by the EPE bit in the Status Register. “Write Enable” on page 21) to set the Write Enable Latch (WEL) bit of the Status 29), then the Byte/Page Program command will not be executed and the “Protect Sector” on page 23 time to determine if the BP PP AT25DL081 [DATASHEET] 14 8732E–DFLASH–1/2013 ...
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... Input Input Data Byte 2 Data Byte MSB MSB AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 15 ...
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... EPE bit in the Status Register. Figure 8-5. Block Erase SCK Opcode MSB High-impedance SO . BLKE Address Bits A23- MSB AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 time to BLKE 16 ...
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... The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly erase error occurs, it will be indicated by the EPE bit in the Status Register. Figure 8-6. Chip Erase SCK Opcode MSB High-impedance time to CHPE AT25DL081 [DATASHEET] 17 8732E–DFLASH–1/2013 ...
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... WEL bit in the Status Register, as well as the SPRL (Sector Protection Registers Locked) and SLE (Sector Lockdown Enabled) bits, will not be affected. Table 8-1 outlines the operations that are allowed and not allowed 41) is performed while a sector is erase suspended, the suspend operation will AT25DL081 [DATASHEET] 18 8732E–DFLASH–1/2013 ...
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... Erase Suspend Allowed Not Allowed Not Allowed Allowed Allowed Allowed Allowed Allowed Not Allowed Not Allowed Not Allowed Allowed Not Allowed Not Allowed Allowed Not Allowed Allowed Allowed Not Allowed Allowed Allowed Not Allowed Not Allowed AT25DL081 [DATASHEET] 19 8732E–DFLASH–1/2013 ...
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... RDY/BSY bit or the appropriate bit in the Status Register to determine if the previously suspended program or erase operation has resumed. Figure 8-8. Program/Erase Resume SCK Opcode MSB High-impedance SO time before issuing the Program/Erase Suspend command must RES AT25DL081 [DATASHEET] 20 8732E–DFLASH–1/2013 ...
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... WEL bit will not change. Figure 9-1. Write Enable SCK Opcode MSB High-impedance AT25DL081 [DATASHEET] 21 8732E–DFLASH–1/2013 ...
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... WEL bit will not change. Figure 9-2. Write Disable SCK Opcode MSB High-impedance AT25DL081 [DATASHEET] 22 8732E–DFLASH–1/2013 ...
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... Register back to a Logical 0 and return to the idle state once the CS pin has been deasserted. Figure 9-3. Protect Sector SCK SI (SIO MSB High-impedance SO (SOI Opcode Address Bits A23- MSB AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 23 ...
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... High-impedance SO (SOI) Table 9-1 for Sector Protection Register values). Every physical sector of the device Opcode Address Bits A23- MSB AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 24 ...
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... WP pin and the sector protection status. Please refer to “Read Status Register” on page 35 can be read for bits and 2. “Write Status Register Byte 1” on page 39 and Table 11-1 on page 35 for details on the Status Register format and what values for command AT25DL081 [DATASHEET] 25 8732E–DFLASH–1/2013 ...
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... WP pin is high. To perform a Global Protect/Unprotect, the Write Status Register command must be issued again after the SPRL bit has been changed from New SPRL Value AT25DL081 [DATASHEET] 26 8732E–DFLASH–1/2013 ...
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... Therefore, if operating at clock frequencies Address Bits A23- MSB D MSB “Read Status Data Byte MSB AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 27 ...
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... Sector commands. Global Protect and Unprotect can also be performed. Locked in current state. Protect and Unprotect Sector Can be modified from commands will be ignored. Global Protect and Unprotect cannot be performed. , the SPRL bit in the Status Register CC Sector (1) n Unprotected Protected AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 28 ...
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... Sector Lockdown command will be ignored and the device will reset the WEL bit in the Status Register back to a Logical 0 and return to the idle state once the CS pin has been deasserted. 40). To issue the Sector Lockdown command, the CS pin must first be LOCK AT25DL081 [DATASHEET addition, the WEL bit in the “Freeze Sector Lockdown 29 ...
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... MSB MSB Address Bits A23-A0 Confirmation Byte MSB MSB AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 30 ...
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... Address Bits A23- MSB MSB Don't Care Data Byte MSB AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 D D MSB 31 ...
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... Security Register will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is internally self-timed and should take place in a time of t Security Register. Security Register Byte Number Adesto Factory Programmed . It is not possible to suspend the programming of the OTP OTPP . . . 126 127 AT25DL081 [DATASHEET] 32 8732E–DFLASH–1/2013 ...
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... MSB High-impedance Address Bits A23-A0 Data In Byte MSB MSB OTPP 39 Data In Byte MSB AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 33 ...
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... To read the OTP Security Register, the CS pin must first be asserted and then the Address Bits A23- MSB MSB 35 36 Don't Care Data Byte MSB AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 MSB 34 ...
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... Reserved for future use All sectors are software protected (all Sector Protection Registers are 1 – default) Device is not write enabled (default) Device is write enabled Device is ready Device is busy with an internal operation AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 35 ...
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... Sector Lockdown and Freeze Sector Lockdown 1 State commands are enabled 0 No sectors are program suspended (default sector is program suspended 0 No sectors are erase suspended (default sector is erase suspended 0 Device is ready R 1 Device is busy with an internal operation AT25DL081 [DATASHEET] 36 8732E–DFLASH–1/2013 ...
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... Byte/Page Program, Erase, Protect Sector, Unprotect Sector, Sector Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, Write Status Register, or Write Configuration Register command must have been clocked into the device. AT25DL081 [DATASHEET] 37 8732E–DFLASH–1/2013 ...
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... Status Register Status Register Byte 1 Byte MSB MSB Status Register Byte MSB AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 38 ...
Page 39
... SCK Opcode MSB High-impedance SO for more details. Bit 5 Bit 4 Bit 3 Global Protect/Unprotect Status Register In Byte MSB Bit 2 Bit 1 Bit AT25DL081 [DATASHEET] 39 8732E–DFLASH–1/2013 ...
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... High-impedance SO Table Bit 5 Bit 4 Bit 3 X RSTE SLE Status Register In Byte MSB 11-4). Any additional data bytes sent to the Bit 2 Bit 1 Bit AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 X 40 ...
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... Reset operation will be performed. Figure 12-1. Reset SCK Opcode MSB High-impedance Confirmation Byte MSB . Since the RST AT25DL081 [DATASHEET] 41 8732E–DFLASH–1/2013 ...
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... JEDEC code: 0001 1111 (1Fh for Adesto) Family code: 010 (SPI or Dual-I/O) 45h Density code: 00101 (8-Mbit) Sub code: 000 (Standard series) 02h Product variant:00010 Hex Value Details RFU: Reserved for future use 00h Device revision:00000 (Initial version) AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 42 ...
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... Opcode SI 9Fh High-impedance SO 1Fh Manufacturer ID Note: Each transition shown for SI and SO represents one byte (8 bits 45h 02h 01h Device ID Device ID EDI Byte 1 Byte 2 String Length 00h EDI Data Byte 1 AT25DL081 [DATASHEET] 43 8732E–DFLASH–1/2013 ...
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... Deep Power-Down mode. Figure 12-3. Deep Power-Down SCK Opcode MSB High-impedance SO Active Current I CC Standby Mode Current t EDPD Deep Power-Down Mode Current . EDPD AT25DL081 [DATASHEET] 44 8732E–DFLASH–1/2013 ...
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... Deep Power-Down mode. Figure 12-4. Resume from Deep Power-Down SCK Opcode MSB High-impedance SO Active Current I CC Deep Power-Down Mode Current t RDPD Standby Mode Current AT25DL081 [DATASHEET] 45 8732E–DFLASH–1/2013 ...
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... If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted and the device will reset the WEL bit in the Status Register back to the Logical 0 state. Figure 12-5. Hold Mode CS SCK HOLD Hold Hold Hold AT25DL081 [DATASHEET] 46 8732E–DFLASH–1/2013 ...
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... SCK to latch the data in. Similarly, the host controller should clock its data out on the rising edge of SCK in order to give the AT25DL081 a full clock cycle to latch the incoming data in on the next rising edge of SCK. ...
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... Max CMOS levels CMOS levels OUT 0 1.6mA Min -100μ Min AT25DL081 [DATASHEET] AT25DL081 -40C to 85C 1.65V to 1.95V Typ Max Units 25 35 μ μ ...
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... Units 100 MHz 85 MHz 40 MHz 85 MHz Min Max Units 4.3 ns 4.3 ns 0.1 V/ns 0.1 V/ 100 200 μs 3 μs 35 μs 30 μs AT25DL081 [DATASHEET] 49 8732E–DFLASH–1/2013 ...
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... Program Erase Program Erase Measurement CC Level Min Typ Max Units 1.0 3 μs 50 200 250 600 ms 550 950 10 16 sec 10 20 μ μ 200 500 μs 200 ns Min Max Units 70 μ 1.2 1.55 V AT25DL081 [DATASHEET] 50 8732E–DFLASH–1/2013 ...
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... SI 0 MSB of Write Status Register Byte 1 Opcode High-impedance SO t CSLH t t CLKL CSHS LSB t CLKH WPH LSB of Write Status Register Data Byte t CSH t CSHH MSB t t CLKL DIS MSB MSB of Next Opcode AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 51 ...
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... Figure 15-4. HOLD Timing – Serial Input CS SCK t HHH HOLD SI High-impedance SO Figure 15-5. HOLD Timing – Serial Output CS SCK t HHH HOLD SI t HLQZ SO t HLS t t HLH HHS t HLS t t HLH HHS t HHQX AT25DL081 [DATASHEET] 52 8732E–DFLASH–1/2013 ...
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... Ordering Information 16.1 Ordering Code Detail Designator Product Family Device Density 08 = 8-megabit Interface 1 = Serial 16.2 Green Package Options (Pb/halide-free/RoHS-compliant) Ordering Codes (1) AT25DL081-SSHN-B (1) AT25DL081-SSHN-T (1) AT25DL081-MHN-Y (1) AT25DL081-MHN-T (1) AT25DL081-UUN-T 8-WLCSP Notes: 1. The shipping carrier option code is not marked on the devices. 2. Please contact Adesto for 8-ball dBGA (WLCSP) package outline drawing. ...
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... Small Outline (JEDEC SOIC Ø END VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 1.35 – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 Ø Ø 0° – 8° GPC DRAWING NO. REV. SWB 8S1 AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 6/22/ ...
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... Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) C SIDE VIEW y A1 COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM 0.45 0.55 0.60 A1 0.00 0.02 0.05 b 0.35 0.40 0.48 C 0.152 REF D 4.90 5.00 5.10 D2 3.80 4.00 4.20 E 5.90 6.00 6.10 E2 3.20 3.40 3.60 e 1.27 L 0.50 0.60 0.75 y 0.00 – 0.08 K 0.20 – – 4/15/08 GPC DRAWING NO. YFG 8MA1 AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 REV ...
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... C D 0.500 Signal x-coord y-coord CSBPAD -0.250 0.750 vdd! 0.250 0.750 SOPAD -0.250 0.250 HLDBPAD 0.250 0.250 WPBPAD -0.250 -0.250 SCKPAD 0.250 -0.250 gnd! -0.250 -0.750 SIPAD 0.250 -0.750 DRAWING NO. GPC 8U-4 GFB AT25DL081 [DATASHEET] 8732E–DFLASH–1/2013 3/22/12 REV ...
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... Decreased Read Array (03h opcode) clock frequency from 50MHz to 40MHz. Decreased Chip Erase typical time from 12 sec to 10 sec and maximum time from 25 sec to 16 sec. Various typopgraphical edits throughout document. 8732A 11/2011 Initial document release. AT25DL081 [DATASHEET] 57 8732E–DFLASH–1/2013 ...
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... AT25DL081 [DATASHEET] 58 8732E–DFLASH–1/2013 ...
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... Disclaimer: Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...