GLS36VF1601G-70-4I-L1PE Greenliant, GLS36VF1601G-70-4I-L1PE Datasheet - Page 4

• Manufacturer Part Number: GLS36VF1601G-70-4I-L1PE
• Description: Flash 16M Flash 1M SRAM Industrial Temp
• Manufacturer: Greenliant

Specifications of GLS36VF1601G-70-4I-L1PE

• Rohs: yes
• Memory Type: Flash
• Memory Size: 16 Mbit
• Timing Type: Asynchronous
• Access Time: 70 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 15 mA
• Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LFBGA-48

Data Sheet
Erase-Suspend/Erase-Resume Operations
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing a one-byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode no more than 10 µs
after the Erase-Suspend command had been issued. (T
maximum latency equals 10 µs.) Valid data can be read
from any sector or block that is not suspended from an
Erase operation. Reading at address location within erase-
suspended sectors/blocks will output DQ
DQ
operation is allowed except for the sector or block selected
for Erase-Suspend. To resume Sector-Erase or Block-
Erase operation which has been suspended, the system
must issue an Erase-Resume command. The operation is
executed by issuing a one-byte command sequence with
Erase Resume command (30H) at any address in the one-
byte sequence.
Write Operation Status Detection
These devices provide one hardware and two software
means to detect the completion of a Write (Program or
Erase) cycle in order to optimize the system Write cycle
time. The hardware detection uses the Ready/Busy# (RY/
BY#) output pin. The software detection includes two sta-
tus bits: Data# Polling (DQ
End-of-Write detection mode is enabled after the rising
edge of WE#, which initiates the internal Program or Erase
operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Ready/Busy#
(RY/BY#), a Data# Polling (DQ
may be simultaneous with the completion of the Write
cycle. If this occurs, the system may get an erroneous
result, i.e., valid data may appear to conflict with either DQ
or DQ
ous result occurs, the software routine should include a
loop to read the accessed location an additional two (2)
times. If both Reads are valid, then the Write cycle has
completed, otherwise the rejection is valid.
©2010 Greenliant Systems, Ltd.
6
at “1”. While in Erase-Suspend mode, a Program
6
. In order to prevent spurious rejection if an errone-
7
) and Toggle Bit (DQ
7
), or Toggle Bit (DQ
2
toggling and
6
6
) Read
). The
ES
7
4
Ready/Busy# (RY/BY#)
The devices include a Ready/Busy# (RY/BY#) output sig-
nal. RY/BY# is an open drain output pin that indicates
whether an Erase or Program operation is in progress.
Since RY/BY# is an open drain output, it allows several
devices to be tied in parallel to V
resistor. After the rising edge of the final WE# pulse in the
command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.
Byte/Word (BYTE#)
The device includes a BYTE# pin to control whether the
device data I/O pins operate x8 or x16. If the BYTE# pin is
at logic “1” (V
data I/0 pins DQ
and OE#.
If the BYTE# pin is at logic “0”, the device is in x8 data con-
figuration: only data I/O pins DQ
trolled by CE# and OE#. The remaining data pins DQ
DQ
input A
Data# Polling (DQ
When the devices are in an internal Program operation,
any attempt to read DQ
the true data. Once the Program operation is completed,
DQ
any attempt to read DQ
nal Erase operation is completed, DQ
The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block-, or Chip-Erase, the Data# Polling is valid after the ris-
ing edge of sixth WE# (or CE#) pulse. See Figure 11 for
Data# Polling (DQ
flowchart.
16 Mbit Concurrent SuperFlash
14
7
will produce true data. During internal Erase operation,
are at Hi-Z, while pin DQ
-1
for the Least Significant Bit of the address bus.
GLS36VF1601E / GLS36VF1602E
IH
) the device is in x16 data configuration: all
0
-DQ
7
) timing diagram and Figure 25 for a
15
7
7
7
are active and controlled by CE#
will produce a ‘0’. Once the inter-
)
will produce the complement of
15
0
DD
-DQ
is used as the address
via an external pull-up
7
7
are active and con-
S71274-05-000
will produce a ‘1’.
05/10
8
-