PCAL9555AHF,128 NXP Semiconductors, PCAL9555AHF,128 Datasheet - Page 10

• Manufacturer Part Number: PCAL9555AHF,128
• Description: Interface - I/O Expanders
• Manufacturer: NXP Semiconductors

Specifications of PCAL9555AHF,128

• Rohs: yes
• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: HWQFN-24
• Operating Current: 160 mA
• Output Current: 25 mA
• Power Dissipation: 200 mW
• Product Type: I/O Expanders

NXP Semiconductors
PCAL9555A
Product data sheet
6.2.8 Pull-up/pull-down enable register pair (46h, 47h)
cleared, assuming there were no additional input(s) that have changed, and bit 4 of the
input port 0 register will read ‘1’. The next read of the input port 0 register bit 4 register
should now read ‘0’.
An interrupt remains active when a non-latched input simultaneously switches state with a
latched input and then returns to its original state. A read of the input register reflects only
the change of state of the latched input and also clears the interrupt. The interrupt is not
cleared if the input latch register changes from latched to non-latched configuration. If the
input pin is changed from latched to non-latched input, a read from the input port register
reflects the current port logic level. If the input pin is changed from non-latched to latched
input, the read from the input register reflects the latched logic level. A register pair write is
described in
Table 17.
Table 18.
These registers allow the user to enable or disable pull-up/pull-down resistors on the I/O
pins. Setting the bit to logic 1 enables the selection of pull-up/pull-down resistors. Setting
the bit to logic 0 disconnects the pull-up/pull-down resistors from the I/O pins. Also, the
resistors will be disconnected when the outputs are configured as open-drain outputs (see
Section
resistor. A register pair write is described in
described in
Table 19.
Table 20.
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
6.2.12). Use the pull-up/pull-down registers to select either a pull-up or pull-down
Input latch port 0 register (address 44h)
Input latch port 1 register (address 45h)
Pull-up/pull-down enable port 0 register (address 46h)
Pull-up/pull-down enable port 1 register (address 47h)
PE0.7
PE1.7
L0.7
L1.7
Section 7.1
Section
7
0
7
0
7
1
7
1
All information provided in this document is subject to legal disclaimers.
Low-voltage 16-bit GPIO with Agile I/O, interrupt and weak pull-up
7.2.
PE0.6
PE1.6
L0.6
L1.6
Rev. 1 — 3 October 2012
6
0
6
0
6
1
6
1
and a register pair read is described in
PE0.5
PE1.5
L0.5
L1.5
5
0
5
0
5
1
5
1
PE0.4
PE1.4
L0.4
L1.4
Section 7.1
4
0
4
0
4
1
4
1
PE0.3
PE1.3
L0.3
L1.3
3
0
3
0
3
1
3
1
and a register pair read is
PE0.2
PE1.2
L0.2
L1.2
PCAL9555A
2
0
2
0
2
1
2
1
Section
© NXP B.V. 2012. All rights reserved.
PE0.1
PE1.1
7.2.
L0.1
L1.1
1
0
1
0
1
1
1
1
PE0.0
PE1.0
L0.0
L1.0
10 of 46
0
0
0
0
0
1
0
1