PCA9535ECDWR2G ON Semiconductor, PCA9535ECDWR2G Datasheet - Page 15

• Manufacturer Part Number: PCA9535ECDWR2G
• Description: Interface - I/O Expanders 16-BIT I/O EXPANDER
• Manufacturer: ON Semiconductor

Specifications of PCA9535ECDWR2G

• Rohs: yes
• Logic Family: PCA9535
• Number Of I/os: 16
• Maximum Operating Frequency: 400 KHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 55 C to + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-24
• Interface Type: I2C, SMBus
• Interrupt Output: Yes
• Operating Current: 1.65 V to 5.5 V
• Output Current: 50 mA
• Power Dissipation: 600 mW
• Product Type: I/O Expanders

System Configuration
receiving is the ‘receiver’. The device that controls the
Acknowledge
and the STOP conditions from transmitter to receiver is not
limited. Each 8−bit byte is followed by one acknowledge bit.
The acknowledge bit is a HIGH level put on the bus by the
transmitter, whereas the master generates an extra clock
pulse for the acknowledge bit.
acknowledge after the reception of each byte. Also a master
must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter. The
Timing and Test Setup
SDA
SCL
A device generating a message is a ‘transmitter’; a device
The number of data bytes transferred between the START
A slave receiver which is addressed must generate an
P
SDA
SCL
t
BUF
TRANSMITTER/
RECEIVER
MASTER
S
SCL from master
by transmitter
t
HD;STA
data output
data output
by receiver
t
LOW
RECEIVER
SLAVE
t
Figure 18. Definition of Timing on the I
t
condition
r
HD;DAT
Figure 17. Acknowledgement of the I
START
S
Figure 16. System Configuration
TRANSMITTER/
t
HIGH
RECEIVER
http://onsemi.com
SLAVE
1
t
f
15
t
SU;DAT
message is the ‘master’ and the devices which are controlled
by the master are the ‘slaves’ (see Figure 16).
device that acknowledges has to pull down the SDA line
during the acknowledge clock pulse, such that the SDA line
is stable LOW during the HIGH period of the acknowledge
clock pulse; set−up time and hold time must be taken into
account.
by not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event, the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.
2
TRANSMITTER
A master receiver signals an end of data to the transmitter
MASTER
acknowledgement
not acknowledge
2
clock pulse for
2
C Bus
Sr
acknowledge
C Bus
8
TRANSMITTER/
t
RECEIVER
SU;STA
MASTER
t
HD;STA
SLAVE
9
MULTIPLEXER
t
SP
I
2
t
C−BUS
SU;STO
P