PCA9535ECDWR2G ON Semiconductor, PCA9535ECDWR2G Datasheet - Page 6

• Manufacturer Part Number: PCA9535ECDWR2G
• Description: Interface - I/O Expanders 16-BIT I/O EXPANDER
• Manufacturer: ON Semiconductor

Specifications of PCA9535ECDWR2G

• Rohs: yes
• Logic Family: PCA9535
• Number Of I/os: 16
• Maximum Operating Frequency: 400 KHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 55 C to + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-24
• Interface Type: I2C, SMBus
• Interrupt Output: Yes
• Operating Current: 1.65 V to 5.5 V
• Output Current: 50 mA
• Power Dissipation: 600 mW
• Product Type: I/O Expanders

Table 5. AC ELECTRICAL CHARACTERISTICS
PORT TIMING: C
INTERRUPT TIMING: C
10. t
11. t
12. C
13. A master device must internally provide a hold time of al least 300 ns for the SDA signal (refer to V
14. The maximum t
15. Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
t
RST(INT_N)
Symbol
t
t
t
t
t
t
t
t
V(INT_N)
SU:STO
HD:DAT
VD:ACK
HD:STA
SU:STA
VD:DAT
SU:DAT
t
t
t
the undefined region SCL’s falling edge.
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
t
SU(D)
t
f
t
HIGH
LOW
VD:ACK
VD:DAT
V(Q)
H(D)
SCL
BUF
t
SP
b
t
t
f
r
= total capacitance of one bus line in pF.
= minimum time for SDA data out to be valid following SCL LOW.
= time for Acknowledgment signal from SCL LOW to SDA (out) LOW.
SCL Clock Frequency
Bus−Free Time between a STOP and START
Condition
Hold Time (Repeated) START Condition
Setup Time for a Repeated START Condition
Setup Time for STOP Condition
Data Hold Time
Data Valid Acknowledge Time (Note 10)
Data Valid Time (Note 11)
Data Setup Time
LOW Period of SCL
HIGH Period of SCL
Fall Time of SDA and SCL (Notes 13 and 14)
Rise Time of SDA and SCL
Pulse Width of Spikes Suppressed by Input
Filter (Note 15)
Data Output Valid Time (V
Data Input Setup Time
Data Input Hold Time
Data Valid Time
Reset Delay Time
L
f
v 100 pF (See Figures 6, 9 and 10)
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
L
v 100 pF (See Figures 9 and 10)
Parameter
(V
f
.
(V
DD
DD
DD
= 1.65 V to 2.3 V)
= 4.5 V to 5.5 V)
= 2.3 V to 4.5 V)
V
http://onsemi.com
DD
= 1.65 V to 5.5 V; T
Standard Mode
Min
300
250
100
6
4.7
4.0
4.7
4.0
0.3
4.7
4.0
0
0
1
1000
Max
3.45
300
200
350
550
0.1
50
4
4
A
= −55°C to +125°C, unless otherwise specified.
(Note 12)
(Note 12)
0.1C
0.1C
20 +
20 +
Min
100
100
1.3
0.6
0.6
0.6
0.1
1.3
0.6
50
0
0
1
Fast Mode
b
b
IL
of the SCL signal) in order to bridge
Max
300
300
200
350
550
0.4
0.9
50
4
4
0.26
0.26
0.26
0.05
0.26
Min
100
Fast Mode +
0.5
0.5
50
50
0
0
1
f
Max
0.45
is specified at
450
120
120
200
350
550
1.0
50
4
4
MHz
Unit
ms
ms
ms
ms
ns
ms
ns
ns
ms
ms
ns
ns
ns
ns
ns
ms
ms
ms