PCA9535ECDTR2G ON Semiconductor, PCA9535ECDTR2G Datasheet - Page 11

• Manufacturer Part Number: PCA9535ECDTR2G
• Description: Interface - I/O Expanders 16-BIT I/O EXPANDER
• Manufacturer: ON Semiconductor

Specifications of PCA9535ECDTR2G

• Product Category: Interface - I/O Expanders
• Rohs: yes
• Logic Family: PCA9535
• Number Of I/os: 16
• Maximum Operating Frequency: 400 KHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 55 C to + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Interface Type: I2C, SMBus
• Interrupt Output: Yes
• Operating Current: 100 uA
• Output Current: 50 mA
• Power Dissipation: 600 mW
• Product Type: I/O Expanders

Writing to the Port Registers
master must first send the device address with the least
significant bit set to logic 0 (see Figure 5 “PCA9535E and
PCA9535EC device address”). The command byte is sent
after the address and determines which registers will receive
the data following the command byte.
PCA9535E/PCA9535EC. These registers are configured to
Reading the Port Registers
master must first send the PCA9535E/PCA9535EC address
with the least significant bit set to logic 0 (see Figure 5
“PCA9535E and PCA9535EC device address”). The
command byte is sent after the address and determines
which register will be accessed.
this time, the least significant bit is set to logic 1. Data from
the register defined by the command byte will then be sent
write to port
SDA
SCL
from port 0
from port 1
To transmit data to the PCA9535E/PCA9535EC, the bus
There
To read data from the PCA9535E/PCA9535EC, the bus
After a restart, the device address must be sent again, but
data out
data out
SDA
S A6
SCL
START condition
1
S A6
START condition
A5 A4 A3
2
1
are
slave address
3
A5 A4 A3
2
4
slave address
3
5
A2 A1 A0 0
eight
4
6
5
A2 A1 A0 0
7
6
R/W acknowledge
8
7
registers
R/W acknowledge
9
A
from slave
8
9
0
A
from slave
Figure 7. Write to Configuration Registers
0
0
Figure 6. Write to Output Port Registers
command byte
0
0
within
command byte
0
0
0
0
BUS TRANSACTIONS
0
1
http://onsemi.com
0
1
the
1
0
0
A
acknowledge
from slave
11
MSB
A
acknowledge
from slave
operate as four register pairs: Input Ports, Output Ports,
Polarity Inversion Ports, and Configuration Ports. Data
bytes are sent alternately to each register in a register pair
(see Figures 6 and 7). For example, if one byte is sent to
Output Port 1 (register 3), then the next byte will be stored
in Output Port 0 (register 2). There is no limitation on the
number of data bytes sent in one write transmission. In this
way, each 8−bit register may be updated independently of
the other registers.
by the PCA9535E/PCA9535EC (see Figures 8, 9 and 10).
Data is clocked into the register on the falling edge of the
acknowledge clock pulse. After the first byte is read,
additional bytes may be read but with data alternately
coming from each register in the pair. For example, if you
read Input Port 1, then the next byte read would be
Input Port 0. There is no limitation on the number of data
bytes received in one read transmission but the bus master
must not acknowledge the data for the final byte received.
0.7
data to register
data to port 0
DATA 0
DATA 0
t
v(Q)
LSB
0.0
A
acknowledge
from slave
A
acknowledge
from slave
MSB
1.7
data to register
data to port 1
DATA 1
DATA 1
DATA VALID
t
v(Q)
LSB
1.0
A
A
condition
condition
STOP
STOP
P
P