AT91SAM9261S-CU Atmel, AT91SAM9261S-CU Datasheet - Page 13

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AT91SAM9261S-CU

Manufacturer Part Number
AT91SAM9261S-CU
Description
ARM Microcontrollers - MCU BGA IND TEMP
Manufacturer
Atmel
Series
91Sr
Datasheet

Specifications of AT91SAM9261S-CU

Product Category
ARM Microcontrollers - MCU
Rohs
yes
Core
ARM926EJ-S
Data Bus Width
32 bit
Maximum Clock Frequency
190 MHz
Program Memory Size
32 KB
Data Ram Size
16 KB
Operating Temperature Range
- 40 C to + 85 C
Package / Case
BGA-217
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USB
Length
15 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
96
Number Of Timers
4
Program Memory Type
ROM
Factory Pack Quantity
126
Supply Voltage - Max
1.32 V, 3.6 V
Supply Voltage - Min
1.08 V, 1.65 V, 2.7 V, 3 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM9261S-CU
Manufacturer:
ATMEL
Quantity:
71
7. Processor and Architecture
7.1
6242ES–ATARM–11-Sep-09
ARM926EJ-S Processor
• RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java
• Two Instruction Sets
• DSP Instruction Extensions
• 5-Stage Pipeline Architecture:
• 16 Kbyte Data Cache, 16 Kbyte Instruction Cache
• Write Buffer
• Standard ARM v4 and v5 Memory Management Unit (MMU)
• Bus Interface Unit (BIU)
acceleration
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
– Virtually-addressed 4-way Associative Cache
– Eight words per line
– Write-through and Write-back Operation
– Pseudo-random or Round-robin Replacement
– Main Write Buffer with 16-word Data Buffer and 4-address Buffer
– DCache Write-back Buffer with 8-word Entries and a Single Address Entry
– Software Control Drain
– Access Permission for Sections
– Access Permission for large pages and small pages can be specified separately for
– 16 embedded domains
– Arbitrates and Schedules AHB Requests
– Separate Masters for both instruction and data access providing complete AHB
– Separate Address and Data Buses for both the 32-bit instruction interface and the
– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
each quarter of the page
system flexibility
32-bit data interface
(Words)
AT91SAM9261S
13

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