MAX3890ECB-D Maxim Integrated, MAX3890ECB-D Datasheet
MAX3890ECB-D
Related parts for MAX3890ECB-D
MAX3890ECB-D Summary of contents
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... Conversion o Clock Synthesis for 2.5Gbps o Multiple Clock Reference Frequencies (155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz) o LVDS Parallel Clock and Data Inputs o Additional High-Speed Output for System Loopback Testing Applications PART MAX3890ECB *EP = Exposed pad Pin Configuration appears at end of data sheet. +3.3V TTL CLKSET V SOS CC SDO+ ...
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SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs ABSOLUTE MAXIMUM RATINGS Terminal Voltage (with respect to GND) V .......................................................................-0.5V to +5V CC All Inputs, FIL+, FIL- ...............................-0. Output Current LVDS Outputs (PCLKO±)................................................10mA PECL Outputs (SDO±, ...
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SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs DC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V, differential LVDS loads = 100Ω ±1%, PECL loads = 50Ω ± -40°C to +85°C, unless ...
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SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs (V = +3.3V, PECL loads = 50Ω ±1 SUPPLY CURRENT vs. TEMPERATURE 200 180 160 140 120 PECL OUTPUTS UNTERMINATED 100 -50 - TEMPERATURE ...
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SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs PIN NAME 1, 17, 33, 48, 49, 63 GND 10, 13 14, 32, 56, 60 SLBO- 4 SLBO+ 6 SOS 8 SCLKO- ...
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SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs Detailed Description The MAX3890 converts 16-bit-wide, 155Mbps data to 2.5Gbps serial data (Figure 1 composed of a 16- bit parallel input register, a 16-bit shift register, control ...
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SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs PCLKO PCLKI PARALLEL VALID PARALLEL DATA* INPUT DATA (PDI_) SERIAL OUTPUT DATA (SDO) NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLKO = (PCLKO+) - (PCLKO-). *PDI 15 = D15; ...
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SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs V CC 50Ω 50Ω GND OUTPUT CIRCUIT Figure 3. Current-Mode Logic Applications Information Alternative PECL-Output Termination Figure 4 shows alternative PECL-output termination methods. Use Thevenin-equivalent termination when a (V ...
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SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs PD+ D PD- V PD- SINGLE-ENDED OUTPUT V PD PD+ PD- 0V (DIFF) DIFFERENTIAL OUTPUT Figure 5. Driver Output Levels _______________________________________________________________________________________ 100Ω L ...
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SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs TOP VIEW GND SLBO- 3 SLBO SOS SCLKO- 8 SCLKO SDO- 11 SDO+ ...
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SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs ______________________________________________________________________________________ Package Information 11 ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products ...