FT220XS-U FTDI, FT220XS-U Datasheet - Page 17
FT220XS-U
Manufacturer Part Number
FT220XS-U
Description
USB Interface IC USB to 4 bit SPI / FT1248 IC SSOP-16
Manufacturer
FTDI
Datasheet
1.FT220XS-R.pdf
(48 pages)
Specifications of FT220XS-U
Rohs
yes
Tradename
X-Chip
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When CPOL is 1, the idle state of the clock is high. When CPOL is 0, the idle state of the clock is low. It
should be noted that clock phase and polarity need to be identical for the master and attached slave
device.
5.4.1 CPHA = 1
When CPHA is set to ‘1’, the first edge after CS# goes low will be used to shift (or drive) the first data bit
onto MIOSIO. Every odd numbered edge after this will shift out the next data bit. Incoming data will be
sampled on the second or trailing SCLK edge and every even edge thereafter.
Figure 5.3
Figure 5.3: FT1248 Clock Format CPHA = 1
Note:
Note:
SCK (CPOL = 0)
SCK (CPOL = 1)
SCK Edge No.
CPHA = 1
Sample
MISO
MOSI
SS_n
The CPOL value may be selected in the MTP memory. This may be done with FT_PROG.
Further information on this interface can be found in AN_167_FT1248 Parallel Serial Interface
Basics from the FTDI website www.ftdichip.com.
shows this for both CPOL = 0 and CPOL = 1.
end of idle
Copyright © 2013 Future Technology Devices International Limited
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FT220X USB 4-BIT SPI/FT1248 IC Datasheet
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Document No.: FT_000629 Clearance No.: FTDI# 262
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Version 1.2
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