AT89LP51ED2-20AU Atmel, AT89LP51ED2-20AU Datasheet - Page 51
AT89LP51ED2-20AU
Manufacturer Part Number
AT89LP51ED2-20AU
Description
8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
Manufacturer
Atmel
Datasheet
1.AT89LP51ED2-20AAU.pdf
(254 pages)
Specifications of AT89LP51ED2-20AU
Rohs
yes
Core
8051
Processor Series
AT89x
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
64 KB
Data Ram Size
256 B
On-chip Adc
Yes
Operating Supply Voltage
2.4 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TQFP-44
Mounting Style
SMD/SMT
Data Rom Size
4 KB
Interface Type
2-Wire, SPI, UART
Number Of Programmable I/os
36
Number Of Timers
3
Program Memory Type
Flash
Factory Pack Quantity
160
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Figure 6-7.
3714A–MICRO–7/11
SIX2
T2X2
T1X2
T0X2
X2
Symbol
SYSTEM CLOCK
Function
UART Clock. In Compatibility Mode, clear for one system clock period per peripheral clock cycle and set for two clock
periods per peripheral clock cycle (only valid when X2 = 1). In Fast Mode, clear for one system clock period and set for
TPS+1 clocks per peripheral clock cycle. This bit affects the generated baud rate during modes 0 and 2.
Timer 2 Clock. In Compatibility Mode, clear for TPS+1 system clock periods per peripheral clock cycle and set for
2(TPS+1) clock periods per peripheral clock cycle. In Fast Mode, clear for one system clock period and set for TPS+1
clocks per peripheral clock cycle. This bit affects the timer increment/decrement rate.
Timer 1 Clock. In Compatibility Mode, clear for TPS+1 system clock periods per peripheral clock cycle and set for
2(TPS+1) clock periods per peripheral clock cycle. In Fast Mode, clear for one system clock period and set for TPS+1
clocks per peripheral clock cycle. This bit affects the timer increment rate.
Timer 0 Clock. In Compatibility Mode, clear for TPS+1 system clock periods per peripheral clock cycle and set for
2(TPS+1) clock periods per peripheral clock cycle. In Fast Mode, clear for one system clock period and set for TPS+1
clocks per peripheral clock cycle. This bit affects the timer increment rate.
CPU Clock. In Compatibility Mode, clear for 12 clock periods per machine cycle and set for 6 clock periods per machine
cycle. In Fast Mode, clear for two clock periods per instruction cycle and set for one clock periods per instruction cycle.
The default state of X2 is set by the X2 Fuse. See
Peripheral Clock Selection
÷(TPS+1)
÷2
Compatibility Mode
÷2
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
AT89LP51RD2/ED2/ID2 Preliminary
Timer 0
Timer 1
Timer 2
Watchdog
PCA
(CPS = 00B)
PCA
(CPS = 01B)
UART
SPI
TWI
Section 24.2 on page
SYSTEM CLOCK
190.
÷(TPS+1)
Fast Mode
÷2
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Timer 0
Timer 1
Timer 2
Watchdog
PCA
(CPS = 00B)
PCA
(CPS = 01B)
UART
SPI
TWI
51
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