C8051F562-IMR Silicon Labs, C8051F562-IMR Datasheet - Page 132
C8051F562-IMR
Manufacturer Part Number
C8051F562-IMR
Description
8-bit Microcontrollers - MCU 50 MIPS 32 kB 2 kB LIN 2.1 SPI
Manufacturer
Silicon Labs
Datasheet
1.C8051F556-IMR.pdf
(302 pages)
Specifications of C8051F562-IMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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C8051F55x/56x/57x
SFR Definition 14.4. CCH0CN: Cache Control
SFR Address = 0xE3; SFR Page = 0x0F
SFR Definition 14.5. ONESHOT: Flash Oneshot Period
SFR Address = 0xBE; SFR Page = 0x0F
132
Name Reserved
Reset
Name
Reset
7:6
4:1
7:4
3:0
Bit
Bit
Type
Type
5
0
Bit
Bit
PERIOD[3:0] Oneshot Period Control Bits.
Reserved
Reserved
CHBLKW
CHPFEN
Name
Unused
Name
R/W
R
7
0
7
0
Must Write 00b
Cache Prefect Enable Bit.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
Must Write 0000b.
Block Write Enable Bit.
This bit allows block writes to Flash memory from firmware.
0: Each byte of a software Flash write is written individually.
1: Flash bytes are written in groups of two.
Reserved
Read = 0000b. Write = don’t care.
These bits limit the internal Flash read strobe width as follows. When the Flash read
strobe is de-asserted, the Flash memory enters a low-power state for the remainder
of the system clock cycle.
R/W
R
6
0
6
0
CHPFEN
R/W
R
5
1
5
0
FLASH
Reserved
R/W
Rev. 1.1
R
4
0
4
0
RDMAX
Function
Reserved
Function
=
R/W
R/W
5ns
3
0
3
1
+
PERIOD 5ns
Reserved
R/W
R/W
2
0
2
1
PERIOD[3:0]
Reserved
R/W
R/W
1
0
1
1
CHBLKW
R/W
R/W
0
0
0
1
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