C8051F912-GUR Silicon Labs, C8051F912-GUR Datasheet
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C8051F912-GUR
Manufacturer Part Number
C8051F912-GUR
Description
8-bit Microcontrollers - MCU 16KB 12ADC
Manufacturer
Silicon Labs
Datasheet
1.C8051F912-GUR.pdf
(2 pages)
Specifications of C8051F912-GUR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Ultra-Low Power
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Supply Voltage: 0.9 to 3.6 V
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12-Bit Analog to Digital Converter
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Two Comparators
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Internal 6-Bit Current Reference
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Development Kit: C8051F912DK
Low-Voltage/Low-Power
160 µA/MHz active current from 1.8–3.6 V @ 25 MHz
10 nA sleep current with data retention; BOD disabled
50 nA sleep current with data retention; BOD enabled
300 nA sleep current with smaRTClock (internal oscillator)
600 nA sleep current with smaRTClock (external crystal)
2 µs wake up from sleep
1.5 µs analog settling time
One-cell mode supports 0.9–3.6 V operation; bypass feature
automatically shuts off the dc-dc converter when not needed
Two-cell mode supports 1.8–3.6 V operation
Built-in dc-dc converter with 1.8 –3.3 V output (65 mW max) for
use in one-cell mode; can supply external devices
Up to 75 ksps 12-bit mode or 300 ksps 10-bit mode
Up to 15 external inputs
External pin or internal VREF (no external capacitor required)
On-chip PGA allows measuring voltages up to twice the
reference voltage
Autonomous Burst Mode with 16-bit automatic averaging
accumulator
Built-in temperature sensor
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (400 nA typical)
Up to 15 Capacitive Touch Sense inputs
Up to ±500 µA; source and sink capability
Enhanced resolution via PWM interpolation
C2CK/RST
VDD/DC+
GND/DC-
XTAL3
XTAL4
DCEN
VBAT
GND
Power Net
Converter
Programming
C2D
Reset/PMU
DC/DC
Power On
Hardware
Analog
Power
Debug /
XTAL1
XTAL2
Wake
Reset
VREG
smaRTClock
Low Power
Precision
24.5 MHz
Oscillator
Oscillator
Oscillator
Oscillator
External
20 MHz
Controller Core
Digital
Power
System Clock
16k Byte ISP Flash
Circuit
Configuration
Program Memory
CIP-51 8051
256 Byte SRAM
512 Byte XRAM
Copyright © 2009 by Silicon Laboratories
SYSCLK
Engine
CRC
SFR
Bus
Internal
VREF
Timers 0,
CP1, CP1A
SPI 0,1
SMBus
Analog Peripherals
6-bit
IREF
12-bit
ADC
UART
1, 2, 3
Digital Peripherals
PCA/
WDT
Port I/O Configuration
Ultra-Low Power, High-Performance MCU
CP0, CP0A
High-Speed 8051 µC Core
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Memory
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Digital Peripherals
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Clock Sources
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On-Chip Debug
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Package Options
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Temperature Range: –40 to +85 °C
Crossbar Control
External
Pipe-lined instruction architecture; executes 70% of instructions
in 1 or 2 system clocks
25 MIPS peak throughput with 25 MHz clock
Expanded interrupt handler
768 bytes internal data RAM (256 + 512)
16 kB Flash; In-system programmable; Full read/write/erase
16 port I/O; All 5 V tolerant with programmable drive strength
Hardware enhanced UART, 2 SPI and SMBus™ serial ports
available concurrently
Low power 32-bit smaRTClock operates down to 0.9 V
Four general purpose 16-bit counter/timers
16-bit programmable counter array (PCA) with six capture/com-
pare modules and watchdog timer
Precision internal oscillators: 24.5 MHz with ±2% accuracy sup-
ports UART operation; spread-spectrum mode for reduced EMI
Low power internal oscillator: 20 MHz
External oscillator: Crystal, RC, C, CMOS clock
smaRTClock oscillator: 32.768 kHz crystal or 16.4 kHz LFO
Can switch between clock sources on-the-fly; useful in power
saving modes
On-chip debug circuitry facilitates full speed, non-intrusive in-
system debug (no emulator required)
Provides 4 breakpoints, single stepping
24-pin QFN (4x4 mm), RoHS compliant
24-pin QSOP (easy to hand solder), RoHS compliant
VREF
functionality over the entire supply range
Comparators
+
-
A
M
U
X
+
Crossbar
-
Decoder
Priority
IREF0
Sensor
VREF
Temp
VDD
GND
Drivers
Drivers
Drivers
Port 0
Port 1
Port 2
P0.0/VREF
P0.1/AGND
P0.2/XTAL1/RTCOUT
P0.3/XTAL2/WAKEOUT
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
P1.0/SCK1
P1.1/MISO1
P1.2/MOSI1
P1.3/NSS1
P1.4
P1.5
P1.6
P2.7/C2D
C8051F912
10.1.2009
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C8051F912-GUR Summary of contents
Page 1
... Low current (400 nA typical Capacitive Touch Sense inputs Internal 6-Bit Current Reference - Up to ±500 µA; source and sink capability - Enhanced resolution via PWM interpolation Development Kit: C8051F912DK Power On Controller Core Reset/PMU 16k Byte ISP Flash Wake Reset Debug / C2CK/RST Programming ...
Page 2
... QSOP 9x6 12-bit 8 768 24p QFN 4x4 10-bit 8 768 24p QSOP 9x6 10-bit 8 768 Copyright © 2009 by Silicon Laboratories C8051F912 Min Typ Max Units 1.8 — 3.6 0.9 — 3.6 — 160 — µA/MHz — .010 — — .050 — ...