C8051F566-IQR Silicon Labs, C8051F566-IQR Datasheet - Page 134
C8051F566-IQR
Manufacturer Part Number
C8051F566-IQR
Description
8-bit Microcontrollers - MCU 50 MIPS 16 kB 2 kB LIN 2.1 SPI
Manufacturer
Silicon Labs
Datasheet
1.C8051F556-IMR.pdf
(302 pages)
Specifications of C8051F566-IQR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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15.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter Stop mode as soon as the
instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital
peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop
mode can only be terminated by an internal or external reset. On reset, the device performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 µs.
15.3. Suspend Mode
Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the CPU and the high-frequency inter-
nal oscillator, and go into Suspend mode as soon as the instruction that sets the bit completes execution.
All internal registers and memory maintain their original data. Most digital peripherals are not active in Sus-
pend mode. The exception to this is the Port Match feature.
Suspend mode can be terminated by three types of events, a port match (described in Section “19.5. Port
Match” on page 177), a Comparator low output (if enabled), or a device reset event. When Suspend mode
is terminated, the device will continue execution on the instruction following the one that set the SUSPEND
bit. If the wake event was configured to generate an interrupt, the interrupt will be serviced upon waking
the device. If Suspend mode is terminated by an internal or external reset, the CIP-51 performs a normal
reset sequence and begins program execution at address 0x0000.
Note: When entering suspend mode, firmware must set the ZTCEN bit in REF0CN (SFR Definition 7.1).
134
Rev. 1.1
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