C8051F343-GMR Silicon Labs, C8051F343-GMR Datasheet - Page 154
![no-image](/images/no-image-200.jpg)
C8051F343-GMR
Manufacturer Part Number
C8051F343-GMR
Description
8-bit Microcontrollers - MCU 48 MIPS 32KB 10 ADC
Manufacturer
Silicon Labs
Datasheet
1.C8051F349-GMR.pdf
(276 pages)
Specifications of C8051F343-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
154
Bits7–0: Output Configuration Bits for P2.7–P2.0 (respectively): ignored if corresponding bit in regis-
Bits7–0: P2SKIP[7:0]: Port2 Crossbar Skip Enable Bits.
R/W
R/W
Bit7
Bit7
ter P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Corresponding P2.n Output is push-pull.
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana-
log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil-
lator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
R/W
R/W
Bit6
Bit6
SFR Definition 15.14. P2MDOUT: Port2 Output Mode
SFR Definition 15.15. P2SKIP: Port2 Skip
R/W
R/W
Bit5
Bit5
R/W
R/W
Bit4
Bit4
Rev. 1.3
R/W
R/W
Bit3
Bit3
R/W
R/W
Bit2
Bit2
R/W
R/W
Bit1
Bit1
R/W
R/W
Bit0
Bit0
SFR Address:
SFR Address:
00000000
00000000
Reset Value
Reset Value
0xA6
0xD6
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