PCA9509AGM,125 NXP Semiconductors, PCA9509AGM,125 Datasheet - Page 7

• Manufacturer Part Number: PCA9509AGM,125
• Description: Interface - Signal Buffers, Repeaters I2CbusSMBus repeater
• Manufacturer: NXP Semiconductors

Specifications of PCA9509AGM,125

• Rohs: yes
• Operating Supply Voltage: 0.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Package / Case: XQFN-8
• Logic Type: I2C, SMBus
• Maximum Clock Frequency: 400 KHz
• Maximum Operating Frequency: 400 KHz
• Power Dissipation: 100 mW
• Factory Pack Quantity: 4000

NXP Semiconductors
7. Application design-in information
PCA9509A
Product data sheet
When the bus capacitance is high, the current should be set near the maximum current
drive for the weakest part. However, if the bus capacitance is low a lower current/higher
resistor value should be used to keep the rise time from getting so fast that it causes
problems. The A side does not need a pull-up resistor. If one is added, care must be taken
to keep the LOW-level voltage at the A side input below 0.1V
A typical application is shown in
I
devices can be placed on either bus.
When port B of the PCA9509A is pulled LOW by a driver on the I
hysteresis input detects the falling edge when it goes below 0.3V
internal driver on port A to turn on, causing port A to pull down to about 0.2V
port A of the PCA9509A falls, a comparator detects the falling edge when it falls below
0.15V
to ground. In order to illustrate what would be seen in a typical application, refer to
Figure 5
PCA9509A, waveforms shown in
like a normal I
On the A bus side of the PCA9509A, the clock and data lines would have a positive offset
from ground equal to the V
will be pulled to the V
example. At the end of the acknowledge, the level rises only to the LOW level set by the
driver in the PCA9509A for a short delay while the B bus side rises above 0.5V
it continues HIGH. It is important to note that any arbitration or clock stretching events
require that the LOW level on the A bus side at the input of the PCA9509A (V
0.1V
2
Fig 4.
C-bus while the slave is connected to a 3.3 V bus. Both buses run at 400 kHz. Master
CC(A)
CC(A)
and
Typical application
to be recognized by the PCA9509A and then transmitted to the B bus side.
and causes the internal driver on port B to turn on and pull the port B pin down
Figure
2
C-bus transmission.
All information provided in this document is subject to legal disclaimers.
MASTER
CPU
6. If the bus master in
OL
Rev. 1 — 29 February 2012
SDA
SCL
of the master device, which is very close to ground in this
OL
10 kΩ
bus A
0.9 V
of the PCA9509A. After the eighth clock pulse, the data line
0.9 V
Figure
Low power level translating I
Figure 5
A1
A2
EN
V
4. In this example, the CPU is running on a 0.9 V
CC(A)
PCA9509A
would be observed on the B bus. This looks
Figure 4
V
CC(B)
B1
B2
were to write to the slave through the
10 kΩ
bus B
3.3 V
10 kΩ
CC(A)
SDA
SCL
2
2
CC(B)
C-bus/SMBus repeater
.
400 kHz
C-bus, a CMOS
SLAVE
PCA9509A
002aaf973
and causes the
© NXP B.V. 2012. All rights reserved.
CC(A)
IL
CC(B)
) is below
. When
, then
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