TDA8035HN/C1,157 NXP Semiconductors, TDA8035HN/C1,157 Datasheet - Page 10

• Manufacturer Part Number: TDA8035HN/C1,157
• Description: Interface - Specialized SMART CARD INTERFACE
• Manufacturer: NXP Semiconductors

Specifications of TDA8035HN/C1,157

• Rohs: yes
• Factory Pack Quantity: 2450

NXP Semiconductors
TDA8035HN
Product data sheet
COMPANY PUBLIC
8.3 Clock circuitry
To generate the card clock CLK, the TDA8035 can either use an external clock provided
on XTAL1 pin or a crystal oscillator connected on both XTAL1 and XTAL2 pins. The
TDA8035 automatically detects when an external clock is provided on XTAL1.
Consequently, there is no need for an extra pin to configure the clock source (external
clock or crystal).
The automatic clock source detection is performed on each activation command
(CMDVCCN pin falling edge). During a time window defined by the internal oscillator, the
presence of an external clock on XTAL1 pin is checked. If a clock is detected, the crystal
oscillator is kept stopped, else, the crystal oscillator is started. It is mandatory when an
external clock is used, that the clock is applied on XTAL1 before CMDVCCN falling edge
signal.
The frequency is chosen as f
CLKDIV2. Both selection inputs are not changed simultaneously. A minimum of 10 ns is
required between changes on CLKDIV1 and CLKDIV2.
The frequency change is synchronous, which means that during transition, no pulse is
shorter than 45 % of the smallest period. This ensures that the first and last clock pulse
around the change has the correct width. When changing the frequency dynamically, the
change is effective for only 10 periods of XTAL1 after the command.
The duty cycle on pin CLK is between 45 % and 55 %:
Table 4.
CLKDIV1
0
0
1
1
Fig 6.
•
•
When an external clock is used on XTAL1 pin and f
between 48 % and 52 %. The subsequent rise and fall times (t
values listed in
CLK frequency is f
It is guaranteed between 45 % and 55 % of the period by the frequency dividers.
Switch external clock
Clock configuration
All information provided in this document is subject to legal disclaimers.
Table
Rev. 2.1 — 3 December 2012
XTAL
7. It has to connect a 56 pF serial capacitor (see
, f
XTAL/2,
XTAL
CLKDIV2
0
1
1
0
, f
Enclkin
XTAL/2
f
XTAL/4
DIGITAL
, f
or f
XTAL/4
MUX
XTAL/8
clkxtal
XTAL
or f
001aan750
:
XTAL/8
XTAL
via the pins CLKDIV1 and
is used, the duty cycle is
TDA8035HN
CLK
f
f
f
f
XTAL/8
XTAL/4
XTAL/2
XTAL
r(i)
Smart card interface
and t
© NXP B.V. 2012. All rights reserved.
f(i)
Figure
) conform to
13).
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