74ALVCH16500DGG,11 NXP Semiconductors, 74ALVCH16500DGG,11 Datasheet - Page 2

• Manufacturer Part Number: 74ALVCH16500DGG,11
• Description: IC UNIV BUS TXRX 18BIT 56TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74ALVCHr

Specifications of 74ALVCH16500DGG,11

• Logic Type: Universal Bus Transceiver
• Number Of Circuits: 18-Bit
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ALVCH16500DG; 74ALVCH16500DG; 935262542112

1. C
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0V; T
NOTES:
ORDERING INFORMATION
56-Pin Plastic TSSOP Type II
1998 Sep 24
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
Current drive
All inputs have bushold circuitry
Output drive capability 50 transmission lines @ 85 C
MULTIBYTE
Low inductance multiple V
and ground bounce
18-bit universal bus transceiver (3-State)
t
C
C
C
C
PHL
P
f
o
I/O
I
PD
PD
PD
D
= output frequency in MHz; V
= C
/t
SYMBOL
PLH
is used to determine the dynamic power dissipation (P
PD
amb
TM
V
PACKAGES
= 25 C; t
CC
24 mA at 3.0 V
flow-through standard pin-out architecture
2
f
i
+ S (C
r
Propagation delay
An, Bn to Bn, An
Input/output capacitance
Input capacitance
Power dissipation capacitance per latch
Power dissi ation ca acitance er latch
= t
CC
f
= 2.5ns
L
and ground pins for minimum noise
V
CC
CC
= supply voltage in V; S (C
2
PARAMETER
f
o
) where: f
TEMPERATURE RANGE
i
= input frequency in MHz; C
–40 C to +85 C
D
in W):
L
V
V
V
V
V
CC
CC
CC
I
I
= GND to V
= GND to V
2
2
= 2.5V, C
= 3.3V, C
DESCRIPTION
The 74ALVCH16500 is a high-performance CMOS product.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OE
OE
inputs. For A-to-B data flow, the device operates in the transparent
mode when LE
CP
data is stored in the latch/flip-flop on the High-to-Low transition of
CP
Low, the outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OE
and CP
High, and OE
To ensure the high impedance state during power up or power
down, OE
OE
minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
f
o
) = sum of outputs.
AB
AB
BA
AB
. When OE
), latch enable (LE
is held at a High or Low logic level. If LE
should be tied to GND through a pulldown resistor; the
L
L
L
BA
CC
CC
= output load capacitance in pF;
= 30pF
= 50pF
OUTSIDE NORTH AMERICA
. The output enables are complimentary (OE
BA
1
1
CONDITIONS
should be tied to V
74ALVCH16500 DGG
BA
AB
AB
is active Low).
is High. When LE
is High, the outputs are active. When OE
AB
Outputs disabled
Outputs enabled
and LE
CC
BA
through a pullup resistor and
AB
74ALVCH16500
), and clock (CP
is Low, the A data is latched if
Product specification
AB
TYPICAL
DWG NUMBER
is Low, the A-bus
3.1
2.9
8.0
4.0
8533-2125 20079
21
3
SOT364-1
AB
AB
and CP
is active
BA
UNIT
AB
AB
, LE
ns
pF
pF
pF
F
BA
is
and
BA
)