CLC2011ISO8X Cadeka Microcircuits, CLC2011ISO8X Datasheet - Page 11

• Manufacturer Part Number: CLC2011ISO8X
• Description: Operational Amplifiers - Op Amps R-R I/O AMP 5.3V/us 4.9MHz 136uA
• Manufacturer: Cadeka Microcircuits

Specifications of CLC2011ISO8X

• Product Category: Operational Amplifiers - Op Amps
• Rohs: yes
• Number Of Channels: 2
• Common Mode Rejection Ratio (min): 81 dB
• Input Offset Voltage: 500 uV
• Input Bias Current (max): 90 nA
• Operating Supply Voltage: 2.5 V to 5.5 V
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Slew Rate: 5.3 V/us
• Shutdown: No
• Output Current: 16 mA
• Maximum Operating Temperature: + 85 C
• Gain Bandwidth Product: 2.5 MHz
• Minimum Operating Temperature: - 40 C
• Supply Current: 136 uA

Data Sheet
Table 1 provides the recommended R
loads. The recommended R
<1dB peaking in the frequency response. The Frequency
Response vs. C
of the CLCx011.
For a given load capacitance, adjust R
tradeoff between settling time and bandwidth. In general,
reducing R
additional overshoot and ringing.
Overdrive Recovery
An overdrive condition is defined as the point when either
one of the inputs or the output exceed their specified
voltage range. Overdrive recovery is the time needed for
the amplifier to return to its normal or linear operating
point. The recovery time varies, based on whether the
input or output is overdriven and by how much the range
is exceeded. The CLCx011 will typically recover in less
than 50ns from an overdrive condition. Figure 7 shows the
CLC1011 in an overdriven condition.
©2009-2010 CADEKA Microcircuits LLC
Figure 6. Addition of R
C
100pF
10pF
20pF
50pF
L
Input
(pF)
S
Table 1: Recommended R
R
will increase bandwidth at the expense of
g
L
+
-
plot, on page 6, illustrates the response
R
100
S
R
0
0
0
f
(Ω)
S
S
for Driving Capacitive Loads
values result in approximately
R
s
-3dB BW (kHz)
C
L
S
for various capacitive
S
2.2
2.4
2.5
2
vs. C
S
R
L
to optimize the
L
Output
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CaDeKa has evaluation
boards to use as a guide for high frequency layout and as
an aid in device testing and characterization. Follow the
steps below as a basis for high frequency layout:
▪
▪
▪
▪
▪
Refer to the evaluation board layouts below for more
information.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
CEB011
CEB002
CEB006
CEB010
CEB018
CEB017
Evaluation Board
Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
Place the 6.8µF capacitor within 0.75 inches of the power pin
Place the 0.1µF capacitor within 0.1 inches of the power pin
Remove the ground plane under and around the part,
especially near the input and output pins to reduce
parasitic capacitance
Minimize all trace lengths to reduce series inductances
-0.5
-1.5
-2.5
2.5
1.5
0.5
-1
-2
-3
3
2
1
0
0
2
Figure 7. Overdrive Recovery
Input
4
#
6
CLC1011 in SC70
CLC1011 in SOT23
CLC2011 in SOIC
CLC2011 in MSOP
CLC4011 in SOIC
CLC4011 in TSSOP
8
Output
Time (us)
10
Products
12
14
www.cadeka.com
G = 5
16
18
20
11