74LVC573ADB-T NXP Semiconductors, 74LVC573ADB-T Datasheet - Page 4

• Manufacturer Part Number: 74LVC573ADB-T
• Description: Latches 3.3V OCTAL D TRANS LATCH 3-S
• Manufacturer: NXP Semiconductors

Specifications of 74LVC573ADB-T

• Product Category: Latches
• Rohs: yes
• Number Of Circuits: 8
• Logic Type: TTL
• Logic Family: LVC
• Polarity: Non-Inverting
• Number Of Output Lines: 8
• High Level Output Current: - 24 mA
• Propagation Delay Time: 3.4 ns at 3.3 V
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.2 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Package / Case: SSOP-20
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8
• Factory Pack Quantity: 1000
• Part # Aliases: 74LVC573ADB,118

NXP Semiconductors
5. Pinning information
Table 2.
74LVC573A
Product data sheet
Symbol
OE
LE
D[0:7]
Q[0:7]
GND
V
Fig 5.
CC
Pin configuration for SO20 and (T)SSOP20
Pin description
GND
OE
D0
D1
D2
D3
D4
D5
D6
D7
10
1
2
3
4
5
6
7
8
9
5.1 Pinning
5.2 Pin description
Pin
1
11
2, 3, 4, 5, 6, 7, 8, 9
19, 18, 17, 16, 15, 14, 13, 12
10
20
573
001aad099
20
19
18
17
16
15
14
13
12
11
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
V
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
All information provided in this document is subject to legal disclaimers.
CC
Rev. 5 — 19 February 2013
Description
output enable input (active LOW)
latch enable input (active HIGH)
data input
data output
ground (0 V)
supply voltage
Fig 6.
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Pin configuration for DHVQFN20 and
DHXQFN20
index area
terminal 1
D0
D1
D2
D3
D4
D5
D6
D7
Transparent top view
2
3
4
5
6
7
8
9
GND
573
(1)
74LVC573A
19
18
17
16
15
14
13
12
001aad100
© NXP B.V. 2013. All rights reserved.
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
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