74LVC573ADB-T NXP Semiconductors, 74LVC573ADB-T Datasheet - Page 5

• Manufacturer Part Number: 74LVC573ADB-T
• Description: Latches 3.3V OCTAL D TRANS LATCH 3-S
• Manufacturer: NXP Semiconductors

Specifications of 74LVC573ADB-T

• Product Category: Latches
• Rohs: yes
• Number Of Circuits: 8
• Logic Type: TTL
• Logic Family: LVC
• Polarity: Non-Inverting
• Number Of Output Lines: 8
• High Level Output Current: - 24 mA
• Propagation Delay Time: 3.4 ns at 3.3 V
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.2 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Package / Case: SSOP-20
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8
• Factory Pack Quantity: 1000
• Part # Aliases: 74LVC573ADB,118

NXP Semiconductors
6. Functional description
Table 3.
[1]
7. Limiting values
Table 4.
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
[1]
[2]
[3]
74LVC573A
Product data sheet
Operating modes
Enable and read register
(transparent mode)
Latch and read register
Latch register and disable outputs
Symbol
V
I
V
I
V
I
I
I
T
P
IK
OK
O
CC
GND
stg
CC
I
O
tot
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
Z = high-impedance OFF-state
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO20 packages: above 70 C the value of P
For (T)SSOP20 packages: above 60 C the value of P
For DHVQFN20 and DHXQFN20 packages: above 60 C the value of P
Functional table
Limiting values
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
[1]
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
Input
OE
L
L
L
L
H
H
All information provided in this document is subject to legal disclaimers.
Conditions
V
V
V
T
tot
amb
I
O
O
< 0
Rev. 5 — 19 February 2013
> V
= 0 V to V
derates linearly with 8 mW/K.
= 40 C to +125 C
tot
CC
derates linearly with 5.5 mW/K.
or V
LE
H
H
L
L
L
L
CC
O
< 0
tot
derates linearly with 4.5 mW/K.
Dn
L
H
l
h
l
h
[1]
[2]
[3]
Min
0.5
50
0.5
-
0.5
-
-
100
65
-
Internal latch Output
L
H
L
H
L
H
Max
+6.5
-
+6.5
50
V
50
100
-
+150
500
CC
74LVC573A
+ 0.5
© NXP B.V. 2013. All rights reserved.
Qn
L
H
L
H
Z
Z
Unit
V
mA
V
mA
V
mA
mA
mA
C
mW
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