74HC595D-Q100,118 NXP Semiconductors, 74HC595D-Q100,118 Datasheet
74HC595D-Q100,118
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74HC595D-Q100,118 Summary of contents
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Rev. 2 — 10 April 2013 1. General description The 74HC595-Q100; 74HCT595-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +125 C 74HC595D-Q100 74HCT595D-Q100 40 C to +125 C 74HC595DB-Q100 74HCT595DB-Q100 40 C to +125 C 74HC595PW-Q100 74HCT595PW-Q100 40 C to +125 C 74HC595BQ-Q100 74HCT595BQ-Q100 5. Functional diagram Fig 1. Functional diagram ...
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... NXP Semiconductors Fig 2. Logic symbol Fig 4. Logic diagram 74HC_HCT595_Q100 Product data sheet 74HC595-Q100; 74HCT595-Q100 8-bit serial-in, serial or parallel-out shift register with output latches ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning +& 4 +&7 4 *1' DDD Fig 5. Pin configuration SO16 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However soldered, the solder land should remain floating or be connected to GND ...
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... NXP Semiconductors 6.2 Pin description Table 2. Pin description Symbol Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 GND Q7S MR SHCP STCP Functional description [1] Table 3. Function table Control Input SHCP STCP ...
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... NXP Semiconductors SHCP DS STCP Q7S Fig 8. Timing diagram 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK I output clamping current ...
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... NXP Semiconductors 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O t/V input transition rise and fall rate T ambient temperature amb 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V LOW-level output voltage all outputs Q7S output bus driver outputs input leakage current ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HCT595-Q100 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage all outputs I O Q7S output bus driver outputs ...
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... NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 74HC595-Q100 t propagation SHCP to Q7S; see pd delay 4 STCP to Qn; see 4 Q7S; see ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t set-up time DS to SHCP; see 4 SHCP to STCP; see Figure 4 hold time DS to SHCP ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t recovery MR to SHCP; see rec time f maximum SHCP and STCP; max frequency see Figure 9 C power MHz dissipation capacitance [1] Typical values are measured at nominal supply voltage. ...
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... NXP Semiconductors SH CP input ST CP input Q n output Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 10. Storage clock to output propagation delays SH CP input D S input output Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance ...
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... NXP Semiconductors Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 12. Master reset to output propagation delays OE input Qn output LOW-to-OFF OFF-to-LOW Qn output HIGH-to-OFF OFF-to-HIGH Measurement points are given in ...
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... NXP Semiconductors negative Test data is given in Table Definitions for test circuit load capacitance including jig and probe capacitance load resistance termination resistance should be equal to the output impedance test selection switch. Fig 14. Test circuit for measuring switching times Table 9. ...
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... NXP Semiconductors 13. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 16 ...
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... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... Revision history Table 11. Revision history Document ID Release date 74HC_HCT595_Q100 v.2 20130410 • Modifications: 74HC595DB-Q100 and 74HCT595DB-Q100 added. 74HC_HCT595_Q100 v.1 20120802 74HC_HCT595_Q100 Product data sheet 74HC595-Q100; 74HCT595-Q100 8-bit serial-in, serial or parallel-out shift register with output latches; Data sheet status Product data sheet Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 5 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 10 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Package outline ...