HEF4052BT-Q100 NXP Semiconductors, HEF4052BT-Q100 Datasheet

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HEF4052BT-Q100

Manufacturer Part Number
HEF4052BT-Q100
Description
Encoders, Decoders, Multiplexers & Demultiplexers 4-ChanMux/Demux 15V
Manufacturer
NXP Semiconductors
Datasheet

Specifications of HEF4052BT-Q100

Product
Multiplexers / Demultiplexers
Logic Family
HEF
Number Of Lines (input / Output)
4 / 4
Supply Voltage - Max
15 V
Supply Voltage - Min
5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SO-16
Minimum Operating Temperature
- 40 C
Number Of Input Lines
4
Number Of Output Lines
4
Operating Temperature Range
- 40 C to + 125 C
Operating Voltage
5 V to 15 V
Power Dissipation
500 mW
Part # Aliases
HEF4052BT-Q100,118
1. General description
2. Features and benefits
3. Applications
The HEF4052B-Q100 is a dual 4-channel analog multiplexer/demultiplexer with common
channel select logic. Each multiplexer/demultiplexer has four independent inputs/outputs
(nY0 to nY3) and a common input/output (nZ). The common channel select logic includes
two select inputs (S1 and S2) and an active LOW enable input (E). Both
multiplexers/demultiplexers contain four bidirectional analog switches, each with one side
connected to an independent input/output (nY0 to nY3) and the other side connected to a
common input/output (nZ). With E LOW, one of the four switches is selected
(low-impedance ON-state) by S1 and S2. With E HIGH, all switches are in the
high-impedance OFF-state, independent of S1 and S2. If break before make is needed,
then it is necessary to use the enable input.
V
and E). The V
nZ) can swing between V
not exceed 15 V. Unused inputs must be connected to V
operation as a digital multiplexer/demultiplexer, V
ground). V
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
DD
HEF4052B-Q100
Dual 4-channel analog multiplexer/demultiplexer
Rev. 1 — 12 July 2012
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
ESD protection:
Complies with JEDEC standard JESD 13-B
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
and V
Specified from 40 C to +85 C and from 40 C to +125 C
MIL-STD-833, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )
SS
EE
are the supply voltage connections for the digital control inputs (S1 and S2,
and V
DD
to V
SS
SS
are the supply voltage connections for the switches.
range is 3 V to 15 V. The analog inputs/outputs (nY0 to nY3, and
DD
as a positive limit and V
EE
EE
is connected to V
as a negative limit. V
DD
, V
SS
, or another input. For
Product data sheet
SS
(typically
DD
 V
EE
may

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HEF4052BT-Q100 Summary of contents

Page 1

HEF4052B-Q100 Dual 4-channel analog multiplexer/demultiplexer Rev. 1 — 12 July 2012 1. General description The HEF4052B-Q100 is a dual 4-channel analog multiplexer/demultiplexer with common channel select logic. Each multiplexer/demultiplexer has four independent inputs/outputs (nY0 to nY3) and a common input/output ...

Page 2

... NXP Semiconductors 4. Ordering information Table 1. Ordering information   All types operate from +125 Type number Package Name HEF4052BT-Q100 SO16 HEF4052BTT-Q100 TSSOP16 5. Functional diagram Fig 1. Functional diagram Fig 2. Schematic diagram (one switch) HEF4052B_Q100 Product data sheet Dual 4-channel analog multiplexer/demultiplexer  ...

Page 3

... NXP Semiconductors Fig 3. Logic symbol HEF4052B_Q100 Product data sheet 1Y0 12 1Y1 14 1Y2 15 1Y3 11 2Y0 1 2Y1 5 2Y2 2 2Y3 4 001aak605 Fig 4. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 HEF4052B-Q100 Dual 4-channel analog multiplexer/demultiplexer ...

Page 4

... NXP Semiconductors LEVEL S1 CONVERTER LEVEL S2 CONVERTER LEVEL E CONVERTER Fig 5. Logic diagram HEF4052B_Q100 Product data sheet Dual 4-channel analog multiplexer/demultiplexer All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 HEF4052B-Q100 1Z 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 2Z 001aak634 © ...

Page 5

... NXP Semiconductors 6. Pinning information 6.1 Pinning HEF4052B-Q100 1 2Y0 2Y2 2Y3 4 2Y1 VEE 7 VSS 8 aaa-003545 Fig 6. Pin configuration SOT109-1 6.2 Pin description Table 2. Pin description Symbol S1, S2 1Y0, 1Y1, 1Y2, 1Y3, 2Y0, 2Y1, 2Y2, 2Y3 12, 14, 15, 11 1Z, 2Z ...

Page 6

... NXP Semiconductors 7. Functional description 7.1 Function table [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level don’t care. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V ...

Page 7

... NXP Semiconductors 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage DD V input voltage I T ambient temperature amb t/V input transition rise and fall rate Fig 8. Operating area as a function of the supply voltages 10. Static characteristics Table 6. Static characteristics ...

Page 8

... NXP Semiconductors Table 6. Static characteristics Symbol Parameter Conditions I OFF-state Z port; S(OFF) leakage all channels OFF; current see Figure 9 Y port; per channel; see Figure 10 I supply current input Sn, E inputs I capacitance 10.1 Test circuits Fig 9 ...

Page 9

... NXP Semiconductors 10.2 On resistance Table 7. ON resistance   200 amb SW SS Symbol Parameter R ON resistance (peak) ON(peak resistance (rail) ON(rail) R ON resistance mismatch ON between channels 10.2.1 On resistance waveform and test circuit Fig 11. Test circuit for measuring R ...

Page 10

... NXP Semiconductors Fig 12. Typical function of input voltage ON 11. Dynamic characteristics Table 8. Dynamic characteristics  for test circuit see amb SS EE Symbol Parameter t HIGH to LOW propagation delay nYn nZ, nYn; see PHL t LOW to HIGH propagation delay Yn nZ, nYn; see ...

Page 11

... NXP Semiconductors Table 8. Dynamic characteristics  for test circuit see amb SS EE Symbol Parameter t OFF-state to LOW PZL propagation delay 11.1 Waveforms and test circuit V DD nYn input PLH nYn V M output V EE Measurement points are given in Fig 13 ...

Page 12

... NXP Semiconductors Test data is given in Table Definitions: DUT = Device Under Test Termination resistance should be equal to output impedance Load capacitance including test jig and probe Load resistance. L Fig 16. Test circuit for measuring switching times Table 10. Test data Input nYn and E ...

Page 13

... NXP Semiconductors 11.2 Additional dynamic parameters Table 11. Additional dynamic characteristics  amb Symbol Parameter THD total harmonic distortion 3 dB frequency response f (3dB)  isolation (OFF-state) iso V crosstalk voltage ct Xtalk crosstalk [ biased Table 12. Dynamic power dissipation P P can be calculated from the formulas shown ...

Page 14

... NXP Semiconductors Fig 19. Test circuit for measuring isolation (OFF-state) a. Test circuit b. Input and output pulse definitions Fig 20. Test circuit for measuring crosstalk voltage between digital inputs and switch HEF4052B_Q100 Product data sheet Dual 4-channel analog multiplexer/demultiplexer and S2 nY0 ...

Page 15

... NXP Semiconductors and S2 nY0 nYn Switch closed condition Fig 21. Test circuit for measuring crosstalk between switches HEF4052B_Q100 Product data sheet Dual 4-channel analog multiplexer/demultiplexer 001aak659 All information provided in this document is subject to legal disclaimers. ...

Page 16

... NXP Semiconductors 12. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 17

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 18

... NXP Semiconductors 13. Abbreviations Table 13. Abbreviations Acronym Description HBM Human Body Model ESD ElectroStatic Discharge MM Machine Model MIL Military 14. Revision history Table 14. Revision history Document ID Release date HEF4052B_Q100_1 20120712 HEF4052B_Q100 Product data sheet Dual 4-channel analog multiplexer/demultiplexer Data sheet status Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — ...

Page 19

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 20

... NXP Semiconductors No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations ...

Page 21

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Limiting values Recommended operating conditions Static characteristics 10.1 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 10.2 On resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 9 10 ...

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