MAX9207EAI-T Maxim Integrated, MAX9207EAI-T Datasheet

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MAX9207EAI-T

Manufacturer Part Number
MAX9207EAI-T
Description
LVDS Interface IC
Manufacturer
Maxim Integrated
Datasheet
The MAX9205/MAX9207 serializers transform 10-bit-
wide parallel LVCMOS/LVTTL data into a serial high-
speed bus low-voltage differential signaling (LVDS)
data stream. The serializers typically pair with deserial-
izers like the MAX9206/MAX9208, which receive the
serial output and transform it back to 10-bit-wide paral-
lel data.
The MAX9205/MAX9207 transmit serial data at speeds
up to 400Mbps and 660Mbps, respectively, over PCB
traces or twisted-pair cables. Since the clock is recov-
ered from the serial data stream, clock-to-data and
data-to-data skew that would be present with a parallel
bus are eliminated.
The serializers require no external components and few
control signals. The input data strobe edge is selected
by TCLK_R/F. PWRDN is used to save power when the
devices are not in use. Upon power-up, a synchroniza-
tion mode is activated, which is controlled by two SYNC
inputs, SYNC1 and SYNC2.
The MAX9205 can lock to a 16MHz to 40MHz system
clock, while the MAX9207 can lock to a 40MHz to
66MHz system clock. The serializer output is held in
high impedance until the device is fully locked to the
local system clock, or when the device is in power-
down mode.
Both the devices operate from a single +3.3V supply,
are specified for operation from -40°C to +85°C, and
are available in 28-pin SSOP packages.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
Cellular Phone Base
Stations
Add Drop Muxes
Digital Cross-Connects
TCLK_R/F
SYNC 1
SYNC 2
TCLK
IN_
10
PLL
General Description
TIMING AND
CONTROL
DSLAMs
Network Switches and
Routers
Backplane Interconnect
Applications
MAX9205
MAX9207
OUT+
OUT-
100Ω
EN
PWRDN
10-Bit Bus LVDS Serializers
TWISTED PAIR
PCB OR
LVDS
BUS
o Standalone Serializer (vs. SERDES) Ideal for
o Framing Bits for Deserializer Resync Allow Hot
o LVDS Serial Output Rated for Point-to-Point and
o Wide Reference Clock Input Range
o Low 140ps (pk-pk) Deterministic Jitter (MAX9207)
o Low 34mA Supply Current (MAX9205)
o 10-Bit Parallel LVCMOS/LVTTL Interface
o Up to 660Mbps Payload Data Rate (MAX9207)
o Programmable Active Edge on Input Latch
o Pin-Compatible Upgrades to DS92LV1021 and
+ Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Pin Configuration and Functional Diagram appear at end of
data sheet.
MAX9205EAI+
M AX 9205E AI/V + -40°C to +85°C 28 SSOP
MAX9207EAI+
Unidirectional Links
Insertion Without System Interruption
Bus Applications
DS92LV1023
100Ω
PART
16MHz to 40MHz (MAX9205)
40MHz to 66MHz (MAX9207)
IN+
IN-
MAX9205/MAX9207
MAX9206
MAX9208
Typical Application Circuit
-40°C to +85°C 28 SSOP
-40°C to +85°C 28 SSOP
RANGE
PLL
TEMP
Ordering Information
RECOVERY
CLOCK
EVALUATION KIT AVAILABLE
TIMING AND
CONTROL
PIN-
PACKAGE
10
19-2029; Rev 2; 10/12
Features
OUT_
REFCLK
EN
LOCK
RCLK
RCLK_R/F
REF CLOCK
RANGE
16 to 40
16 to 40
40 to 66
(MHz)

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MAX9207EAI-T Summary of contents

Page 1

... Pin-Compatible Upgrades to DS92LV1021 and DS92LV1023 PART MAX9205EAI+ -40°C to +85°C 28 SSOP M AX 9205E AI/V + -40°C to +85°C 28 SSOP MAX9207EAI+ -40°C to +85°C 28 SSOP + Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. Pin Configuration and Functional Diagram appear at end of data sheet. Typical Application Circuit ...

Page 2

... Typical values are MIN TYP 2.0 GND -20 = 27Ω 200 286 = 50Ω 250 460 1 0.9 1.15 3 -13 -10 _VCC = 0V or 3.6V -10 16MHz 23 40MHz 34 40MHz 32 66MHz 45 = AVCC MAX UNITS 0.8 V +20 µA 400 mV 600 1 -15 mA +10 µA +10 µ Maxim Integrated ...

Page 3

... OUTPUT Low State to High- Impedance Delay OUTPUT High Impedance to High-State Delay OUTPUT High Impedance to Low-State Delay SYNC Pulse Width PLL Lock Time Bus LVDS Bit Width Serializer Delay Maxim Integrated 10-Bit Bus LVDS Serializers = 27Ω ±1% or 50Ω ±1 10pF SYMBOL CONDITIONS f TCCF ...

Page 4

... Typical values are MIN TYP 16MHz 40MHz 40MHz 66MHz 16MHz 40MHz 40MHz 66MHz WORST-CASE PATTERN SUPPLY CURRENT vs. SUPPLY VOLTAGE TCLK = 40MHz MAX9205 10 3.0 3.3 SUPPLY VOLTAGE (V) = AVCC MAX UNITS 200 140 ps (pk-pk) 140 140 (RMS 3.6 Maxim Integrated ...

Page 5

... The serializer requires a deserializer such as the MAX9206/MAX9208 for a complete data transmission application. Maxim Integrated MAX9205/MAX9207 10-Bit Bus LVDS Serializers FUNCTION A high-state start bit and a low-state stop bit, added internally, frame the 10-bit parallel input data and ensure a transition in the serial data stream ...

Page 6

... Synchronization Mode. SYNC patterns of six 1s and six 0s are transmitted every TCLK cycle for at least 1024 TCLK cycles. Data at IN0–9 are ignored. Data Transmission Mode. IN0–9 and 2 frame bits are L L transmitted every TCLK cycle Output in high-impedance Power-Down High-Impedance State OUTPUTS OUT+, OUT- Maxim Integrated ...

Page 7

... L 2 Figure 1. Output Voltage Definitions TCLK Figure 3. Input Clock Transition Time Requirement Maxim Integrated 10-Bit Bus LVDS Serializers Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by a differential receiver ...

Page 8

... Figure 6. High-Impedance Test Circuit and Timing 8 10pF 80 20% V DIFF 10pF t LHT V = (OUT+) - (OUT-) DIFF t TCP 1.5V 1. 1.5V PARASITIC PACKAGE AND TRACE CAPACITANCE 10pF OUT+ OUT- EN 10pF 1. 50 50% 80 DIFF 20% t HLT 1. 1.5V 13.5Ω +1.1V 13.5Ω 1. 50% 1. 1.1V 50% Maxim Integrated ...

Page 9

... SD TCLK 1.5V OUT± TCLK_ R/F = HIGH Figure 8. Serializer Delay (OUT+) - (OUT-) WAVEFORM t DJIT SUPERIMPOSED RANDOM DATA Figure 9. Definition of Deterministic Jitter (t Maxim Integrated 10-Bit Bus LVDS Serializers IN0 - IN9 SYMBOL TIMING SHOWN FOR TCLK_R/F = HIGH START BIT OUT0 - OUT9 SYMBOL N ...

Page 10

... Figure 12. A 54Ω resistor at the far end ter- minates the bus. This topology allows “broadcast” of data with a minimum of interconnect. SERIALIZED DATA 100Ω ASIC ASIC MAX9206 MAX9206 MAX9208 MAX9208 PARALLEL 100Ω DATA OUT MAX9206 MAX9208 ASIC MAX9206 MAX9208 ASIC MAX9206 MAX9208 54Ω Maxim Integrated ...

Page 11

... MAX9207 MAX9150 REPEATER 100Ω Figure 13. Point-to-Point Broadcast Using MAX9150 Repeater Maxim Integrated 10-Bit Bus LVDS Serializers the primary serializer. The typical close spacing (1in or less) of cards on a backplane reduces the characteris- tic impedance by as much as half the initial, unloaded value ...

Page 12

... RoHS status. PACKAGE TYPE 28 SSOP ASIC MAX9206 MAX9208 Functional Diagram 10 IN_ TCLK_R/F TCLK TIMING AND PLL CONTROL SYNC 1 SYNC 2 MAX9205 MAX9207 Package Information PACKAGE OUTLINE NO. CODE A28+4 21-0056 ASIC MAX9206 MAX9208 54Ω OUT+ OUT- EN PWRDN LAND PATTERN NO. 90-0095 Maxim Integrated ...

Page 13

... Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed ...

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