72V2113L7-5BC IDT, 72V2113L7-5BC Datasheet - Page 22

• Manufacturer Part Number: 72V2113L7-5BC
• Description: FIFO 256Kx18 /512Kx9 3.3V SUPERSYNC II FIFO
• Manufacturer: IDT

Specifications of 72V2113L7-5BC

• Data Bus Width: 18 bit
• Bus Direction: Unidirectional
• Memory Size: 4 Mbit
• Timing Type: Synchronous
• Organization: 256 K x 18
• Maximum Clock Frequency: 133.3 MHz
• Access Time: 7 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 8 V
• Maximum Operating Current: 35 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: BGA-100
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Part # Aliases: IDT72V2113L7-5BC

on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH
on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF
configuration is selected, the PAF is updated on the rising edge of WCLK. See
Figure 20 for Asynchronous Programmable Almost-Full Flag Timing (IDT
Standard and FWFT Mode).
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in Table 2.
in the FIFO. The default setting for this value is stated in Table 2.
(IDT Standard and FWFT Mode), for the relevant timing information.
on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH
on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE
configuration is selected, the PAE is updated on the rising edge of RCLK. See
Figure 21, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Mode), for the relevant timing information.
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
See Figure 19, Synchronous Programmable Almost-Empty Flag Timing
If asynchronous PAF configuration is selected, the PAF is asserted LOW
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
In FWFT mode, the PAE will go LOW when there are n+1 words or less
If asynchronous PAE configuration is selected, the PAE is asserted LOW
TM
NARROW BUS FIFO
TM
NARROW BUS FIFO
22
HALF-FULL FLAG (HF)
beyond half-full sets HF LOW. The flag remains LOW until the difference between
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets HF
HIGH.
HF will go LOW after (D/2 + 1) writes to the FIFO. If x18 Input or x18 Output
bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the
IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D =
262,144 for the IDT72V2103 and 524,288 for the IDT72V2113.
will go LOW after (D-1/2 + 2) writes to the FIFO. If x18 Input or x18 Output bus
Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the
IDT72V2113. If both x9 Input and x9 Output bus Widths are selected,
D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113.
for the relevant timing information. Because HF is updated by both RCLK and
WCLK, it is considered asynchronous.
DATA OUTPUTS (Q
bit wide data.
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
In IDT Standard mode, if no reads are performed after reset (MRS or PRS),
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
See Figure 22, Half-Full Flag Timing (IDT Standard and FWFT Mode),
(Q
0
- Q
17
) data outputs for 18-bit wide data or (Q
0
-Q
n
)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
0
- Q
8
) data outputs for 9-
JUNE 1, 2010