74HC74PW NXP Semiconductors, 74HC74PW Datasheet

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74HC74PW

Manufacturer Part Number
74HC74PW
Description
Flip Flops DUAL D-TYPE POSITIVE EDGE-TRIG
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74HC74PW

Product Category
Flip Flops
Rohs
yes
Number Of Circuits
2
Logic Family
HC
Logic Type
D-Type Edge Triggered Flip-Flop
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Output Type
Differential
Propagation Delay Time
14 ns at 5 V
High Level Output Current
- 5.2 mA
Low Level Output Current
5.2 mA
Supply Voltage - Max
6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOT-402
Minimum Operating Temperature
- 40 C
Number Of Input Lines
1
Number Of Output Lines
1
Factory Pack Quantity
96
Supply Voltage - Min
2 V
Part # Aliases
74HC74PW,112

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74HC74PW
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Company:
Part Number:
74HC74PW
Quantity:
2 080
Company:
Part Number:
74HC74PW
Quantity:
30 000
Part Number:
74HC74PW,118
Manufacturer:
NXP Semiconductors
Quantity:
1 950
Part Number:
74HC74PW,118
Manufacturer:
NXP
Quantity:
17 500
Part Number:
74HC74PW,118
Manufacturer:
NXP
Quantity:
10 000
1. General description
2. Features and benefits
3. Ordering information
Table 1.
Type number
74HC74N
74HCT74N
74HC74D
74HCT74D
74HC74DB
74HCT74DB
Ordering information
Package
Temperature range
40 C to +125 C
40 C to +125 C
40 C to +125 C
The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have
individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary
nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time
requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at
the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to
slower clock rise and fall times. Inputs include clamp diodes that enable the use of current
limiting resistors to interface inputs to voltages in excess of V
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Rev. 4 — 27 August 2012
Input levels:
Symmetrical output impedance
Low power dissipation
High noise immunity
Balanced propagation delays
Specified in compliance with JEDEC standard no. 7A
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
For 74HC74: CMOS level
For 74HCT74: TTL level
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Name
DIP14
SO14
SSOP14
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads; body width
3.9 mm
plastic shrink small outline package; 14 leads; body
width 5.3 mm
CC
.
Product data sheet
SOT27-1
Version
SOT108-1
SOT337-1

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74HC74PW Summary of contents

Page 1

Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 4 — 27 August 2012 1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) ...

Page 2

... NXP Semiconductors Table 1. Ordering information Type number Package Temperature range 40 C to +125 C 74HC74PW 74HCT74PW 40 C to +125 C 74HC74BQ 74HCT74BQ 4. Functional diagram 4 10 1SD 2SD 1CP CP 11 2CP 1RD 2RD ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning +& +&7  &3  *1' Fig 5. Pin configuration for DIP14, SO14 and (T)SSOP14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1RD 1 asynchronous reset-direct input (active LOW data input 1CP 3 clock input (LOW-to-HIGH, edge-triggered) ...

Page 4

... NXP Semiconductors 6. Functional description [1] Table 3. Function table Input nSD nRD [ HIGH voltage level LOW voltage level don’t care. [1] Table 4. Function table Input nSD nRD HIGH voltage level LOW voltage level;  = LOW-to-HIGH transition don’ ...

Page 5

... NXP Semiconductors 8. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/V input transition rise and fall rate 9. Static characteristics Table 7. Static characteristics At recommended operating conditions ...

Page 6

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level output voltage =  LOW-level output voltage input leakage current supply current ...

Page 7

... NXP Semiconductors 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); C Symbol Parameter Conditions 74HC74 t propagation nCP to nQ, nQ; see pd delay Figure nSD to nQ, nQ; see Figure nRD to nQ, nQ ...

Page 8

... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); C Symbol Parameter Conditions t set-up time nD to nCP; see hold time nD to nCP; see maximum nCP; see max frequency 4.5 V ...

Page 9

... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); C Symbol Parameter Conditions t hold time nD to nCP; see 4 maximum nCP; see max frequency power pF MHz dissipation V = GND capacitance [1] All typical values are measured at T ...

Page 10

... NXP Semiconductors 11. Waveforms Q' LQSXW Q&3 LQSXW Q4 RXWSXW Q4 RXWSXW Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 7. Input to output propagation delay, output transition time, clock input pulse width and maximum frequency ...

Page 11

... NXP Semiconductors nCP input nSD input nRD input nQ output nQ output Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 8. Set and reset propogation delays, pulse widths and recovery time Table 9. Measurement points ...

Page 12

... NXP Semiconductors Test data is given in Table Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch. Fig 9. Test circuit for measuring switching times Table 10. Test data Type ...

Page 13

... NXP Semiconductors 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 14

... NXP Semiconductors SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 15

... NXP Semiconductors SSOP14: plastic shrink small outline package; 14 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT337-1 Fig 12 ...

Page 16

... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 17

... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 18

... Dual D-type flip-flop with set and reset; positive edge-trigger Data sheet status Product data sheet The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Product data sheet Product specification All information provided in this document is subject to legal disclaimers. Rev. 4 — ...

Page 19

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 20

... Dual D-type flip-flop with set and reset; positive edge-trigger NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 21

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 Abbreviations ...

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