ISL28118MUZ-T7A Intersil, ISL28118MUZ-T7A Datasheet - Page 17

• Manufacturer Part Number: ISL28118MUZ-T7A
• Description: Precision Amplifiers ISL28118MUZ 40V LW NOISE RAIL-RAIL OUT
• Manufacturer: Intersil

Specifications of ISL28118MUZ-T7A

• Product Category: Precision Amplifiers
• Rohs: yes
• Number Of Channels Per Chip: 1 Channel
• Input Offset Voltage: 25 uV
• Mounting Style: SMD/SMT
• Package / Case: MSOP-8
• Dual Supply Voltage: +/- 3 V, +/- 5 V, +/- 9 V, +/- 12 V, +/- 15 V, +/- 18 V
• Gain Bandwidth Product: 4 MHz
• Maximum Dual Supply Voltage: +/- 20 V
• Maximum Operating Temperature: + 125 C
• Minimum Dual Supply Voltage: - 1.2 V, 1.8 V
• Minimum Operating Temperature: - 55 C
• Operating Supply Voltage: 3 V to 40 V
• Output Current (typ): 40 mA
• Supply Current: 0.85 mA
• Supply Voltage - Max: 40 V
• Supply Voltage - Min: 3 V

*ISL28118_218 Macromodel - covers
following *products
*ISL28118
*ISL28218
*
*Revision History:
* Revision A, LaFontaine February 8th 2011
* Model for Noise, supply currents, CMRR
*120dB f = 40kHz, AVOL 136dB f = 0.5Hz
* SR = 1.2V/us, GBWP 4MHz.
*Copyright 2011 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT”
*Use of this model indicates your acceptance
*with the terms and provisions in the License
*Statement.
*
*Intended use:
*This Pspice Macromodel is intended to give
*typical DC and AC performance
characteristics *under a wide range of
external circuit *configurations using
compatible simulation *platforms – such as
iSim PE.
*
*Device performance features supported by
this *model:
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances,
*Open loop gain and phase,
*Closed loop bandwidth and frequency
*response,
*Loading effects on closed loop frequency
*response,
*Input noise terms including 1/f effects,
*Slew rate,
*Input and Output Headroom limits to I/O
*voltage swing,
*Supply current at nominal specified supply
*voltages,
*
*Device performance features NOT
supported *by this model:
*Harmonic distortion effects,
*Output current limiting (current will limit at
*40mA),
*Disable operation (if any),
*Thermal effects and/or over temperature
*parameter variation,
*Limited performance variation vs. supply
*voltage is modeled,
*Part to part performance variation due to
*normal process parameter spread,
*Any performance difference arising from
*different packaging,
*Load current reflected into the power supply
*current.
* source ISL28118_218 SPICEmodel
*
* Connections:
*
*
*
*
.subckt ISL28118_218 Vin+ Vin-V+ V- VOUT
* source ISL28118_218_presubckt_0
*
*Voltage Noise
E_En
D_D13
D_D14
V_V7
VIN+ 6 2 0 0.3
1 0 0.1
1 2 DN
1 2 DN
+input
|
|
|
|
-input
|
|
|
+Vsupply
|
|
17
-Vsupply
|
output
V_V8
R_R17
*R_R18
*
*Input Stage
Q_Q6
Q_Q7
Q_Q8
Q_Q9
I_I1
I_I2
I_I3
I_IOS
*D_D1
*D_D2
R_R1
R_R2
R_R3
R_R4
C_Cin1
C_Cin2
C_CinDif
*
*1st Gain Stage
G_G1
G_G2
V_V1
V_V2
D_D3
D_D4
R_R5
R_R6
*
*2nd Gain Stage
G_G3
G_G4
V_V3
V_V4
D_D5
D_D6
R_R7
R_R8
C_C1
C_C2
*
*Mid supply Ref
E_E2
E_E3
E_E4
I_ISY
*
*Common Mode Gain Stage with Zero
G_G5
G_G6
G_G7
G_G8
E_EOS
L_L1
L_L2
L_L3
L_L4
R_R9
R_R10
R_R11
R_R12
*
*Pole Stage
G_G9
G_G10
R_R13
FIGURE 51. SPICE NET LIST
V++ 9 DC 80e-6
V++ 7 DC 54E-6
V++ 10 DC 54E-6
ISL28118M
18 V++ 3.18319E-09
20 V-- 3.18319E-09
21 V++ 3.18319E-09
22 V-- 3.18319E-09
4 0 0.1
13 14 -0.91
14 15 -0.96
16 VG -0.91
VG 17 -0.96
V++ 0 V+ 0 1
V-- 0 V- 0 1
VMID V-- V++ V-- 0.5
V+ V- DC 0.85E-3
6 VIN- DC 4e-9
5 6 5e11
VIN- 5 5e11
V-- 8 1000
V-- 11 1000
13 V++ DX
V-- 15 DX
14 V++ 1
V-- 14 1
16 V++ DX
V-- 17 DX
VG V++ 3.7304227e9
V-- VG 3.7304227e9
VG V++ 6.6667E-11
V-- VG 6.6667E-11
19 18 1e-3
11 10 9 PNP_input
8 7 9 PNP_input
V-- VIN- 7 PNP_LATERAL
V-- 12 10 PNP_LATERAL
V++ 14 8 11 0.65897
V-- 14 8 11 0.65897
V++ VG 14 VMID 1.69138e-3
V-- VG 14 VMID 1.69138e-3
V++ 19 5 VMID 1
V-- 19 5 VMID 1
V++ VC 19 VMID 1
V-- VC 19 VMID 1
V++ 23 VG VMID 1.2566e-3
7 10 DBREAK
10 7 DBREAK
VC 21 1e-3
2 0 750
20 19 1e-3
22 VC 1e-3
23 V++ 795.7981
V-- 23 VG VMID 1.2566e-3
V-- VIN- 4.02e-12
V-- 6 4.02e-12
12 6 VC VMID 1
3 0 750
6 VIN- 1.33E-12
R_R14
C_C3
C_C4
*
*Output Stage with Correction Current
Sources
G_G11
G_G12
G_G13
G_G14
D_D7
D_D8
D_D9
D_D10
D_D11
D_D12
V_V5
V_V6
R_R15
R_R16
.model PNP_LATERAL pnp(is=1e-016
bf=250 va=80
+ ik=0.138 rb=0.01 re=0.101 rc=180 kf=0
af=1)
.model PNP_input pnp(is=1e-016 bf=100
va=80
+ ik=0.138 rb=0.01 re=0.101 rc=180 kf=0
af=1)
.model DBREAK D(bv=43 rs=1)
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28118_218
24 VOUT -0.4
VOUT 25 -0.4
23 V++ 10e-12
V-- 23 10e-12
23 24 DX
25 23 DX
V-- 26 DY
V++ 27 DX
V-- 23 795.7981
V++ 26 DX
V-- 27 DY
VOUT V++ 80
V-- VOUT 80
26 V-- VOUT 23 12.5e-3
VOUT V++ V++ 23 12.5e-3
27 V-- 23 VOUT 12.5e-3
V-- VOUT 23 V-- 12.5e-3
May 11, 2011
FN7858.0