24AA02E48-I/SN Microchip Technology, 24AA02E48-I/SN Datasheet - Page 11

• Manufacturer Part Number: 24AA02E48-I/SN
• Description: IC EEPROM 2KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24AA02E48-I/SN

• Memory Size: 2K (256 x 8)
• Package / Case: 8-SOIC (3.9mm Width)
• Format - Memory: EEPROMs - Serial (with MAC Address)
• Memory Type: EEPROM
• Speed: 100kHz, 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Organization: 256 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.1 MHz
• Access Time: 3500 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.7 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 1.8 V , 2.5 V , 3.3 V , 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

8.0
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘
of read operations: current address read, random read
and sequential read.
8.1
The 24AAXXXE48 contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by ‘
access (either a read or write operation) was to address
n
access data from address
slave address with R/W bit set to ‘
issues an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition, and the 24AAXXXE48
discontinues transmission (Figure 8-1).
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24AAXXXE48 as part of a write opera-
tion. Once the word address is sent, the master gener-
ates a Start condition following the acknowledge. This
terminates the write operation, but not before the inter-
nal Address Pointer is set. The master then issues the
control byte again, but with the R/W bit set to a ‘
24AAXXXE48 will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition, and the 24AAXXXE48 will discontinue
transmission (Figure 8-2).
FIGURE 8-1:
 2010 Microchip Technology Inc.
, the next current address read operation would
READ OPERATION
Current Address Read
Random Read
Note:
Bus Activity
Master
SDA Line
Bus Activity
CURRENT ADDRESS READ
1
1
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48.
’. There are three basic types
’. Therefore, if the previous
n + 1
1
. Upon receipt of the
’, the 24AAXXXE48
S
T
A
R
T
S
1
0
1
1 0
’. The
Control
Byte
A2* A1* A0*
24AA02E48/24AA025E48
Select
Chip
Bits
8.3
Sequential reads are initiated in the same way as a
random read, except that once the 24AAXXXE48 trans-
mits the first data byte, the master issues an acknowl-
edge as opposed to a Stop condition in a random read.
This directs the 24AAXXXE48 to transmit the next
sequentially-addressed 8-bit word (Figure 8-3).
To provide sequential reads, the 24AAXXXE48 con-
tains an internal Address Pointer that is incremented by
one upon completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
8.4
The 24AAXXXE48 employs a V
circuit which disables the internal erase/write logic if the
V
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
1
CC
A
C
K
is below 1.5V at nominal conditions.
Sequential Read
Noise Protection
Data (n)
CC
N
o
A
C
K
threshold detector
P
S
T
O
P
DS22124D-page 11