DS2155LC2 Maxim Integrated, DS2155LC2 Datasheet - Page 211

• Manufacturer Part Number: DS2155LC2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Figure 35-7. Transmit-Side ESF Timing
Note 1: TSYNC in frame mode (IOCR1.2 = 0) and double-wide frame sync is not enabled (IOCR1.3 = 0).
Note 2: TSYNC in frame mode (IOCR1.2 = 0) and double-wide frame sync is enabled (IOCR1.3 = 1).
Note 3: TSYNC in multiframe mode (IOCR1.2 = 1).
Note 4: TLINK data (FDL bits) sampled during the F-bit time of odd frame and inserted into the outgoing T1 stream if enabled through TCR1.2.
Note 5: ZBTSI mode is enabled (T1TCR2.1 = 1).
Note 6: TLINK data (Z bits) sampled during the F-bit time of frames 1, 5, 9, 13, 17, and 21 and inserted into the outgoing stream if enabled
Figure 35-8. Transmit-Side Boundary Timing (with Elastic Store Disabled)
Note 1: TSYNC is in the output mode (IOCR1.1 = 1).
Note 2: TSYNC is in the input mode (IOCR1.1 = 0).
Note 3: TCHBLK is programmed to block channel 2.
Note 4: Shown is TLINK/TLCLK in the ESF framing mode.
TSYNC
FRAME#
TSYNC
TSYNC
TSSYNC
TLCLK
TLCLK
TLINK
through T1TCR1.2.
TLINK
TCHBLK
TCHCLK
TSYNC
TSYNC
TLCLK
TLINK
TSER
TCLK
TSIG
2
3
4
1
5
6
1
1
2
3
4
LSB
D/B
2
3
F
4
MSB
5
6
7
8
CHANNEL 1
CHANNEL 1
9 10 11 12
A
B
C/A
211 of 238
13 14 15 16 17 18 19 20 21 22 23 24 1
LSB MSB
D/B
DON'T CARE
CHANNEL 2
CHANNEL 2
A
B
C/A
LSB MSB
D/B
2
3
4
5