74ABT374ADB-T NXP Semiconductors, 74ABT374ADB-T Datasheet

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74ABT374ADB-T

Manufacturer Part Number
74ABT374ADB-T
Description
Flip Flops OCTAL D 3-S
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74ABT374ADB-T

Product Category
Flip Flops
Rohs
yes
Number Of Circuits
1
Logic Family
ABT
Logic Type
D-Type Edge Triggered Flip-Flop
Polarity
Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
3.8 ns
High Level Output Current
- 32 mA
Supply Voltage - Max
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOT-339
Minimum Operating Temperature
- 40 C
Number Of Input Lines
8
Number Of Output Lines
8
Factory Pack Quantity
1000
Supply Voltage - Min
4.5 V
Part # Aliases
74ABT374ADB,118
1. General description
2. Features and benefits
The 74ABT374A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT374A is an 8-bit, edge triggered register coupled to eight 3-state output
buffers. The two sections of the device are controlled independently by the clock input
(CP) and output enable input (OE) control gates.
The register is fully edge-triggered. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS
memories, or MOS microprocessors. The active LOW output enable (OE) controls all
eight 3-state buffers independent of the clock operation.
When OE is LOW, the stored data appears at the outputs. When OE is HIGH, the outputs
are in the high-impedance “OFF” state, which means they will neither drive nor load the
bus.
74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
Rev. 2 — 18 December 2012
8-bit positive edge triggered register
3-state output buffers
Power-on 3-state
Power-on reset
Output capability: +64 mA/32 mA
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
Live insertion/extraction permitted
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Product data sheet

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74ABT374ADB-T Summary of contents

Page 1

Octal D-type flip-flop; positive-edge trigger; 3-state Rev. 2 — 18 December 2012 1. General description The 74ABT374A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT374A is an 8-bit, ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +85 C 74ABT374AN 40 C to +85 C 74ABT374AD 40 C to +85 C 74ABT374ADB 74ABT374APW 40 C to +85 C 4. Functional diagram ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning $%7$ *1'  DDD Fig 4. Pin configuration for DIP20 and SO20 5.2 Pin description Table 2. Pin description Symbol OE D0, D1, D2, D3, D4, D5, D6, D7 GND CP Q0, Q1, Q2, Q3, Q4, Q5, Q6 Functional description [1] Table 3. Function table Operating mode Load and read register ...

Page 4

... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input voltage I V output voltage O I input clamping current IK I output clamping current OK I output current O T junction temperature j T storage temperature ...

Page 5

... NXP Semiconductors Table 6. Static characteristics Symbol Parameter V power-up LOW-level OL(pu) output voltage I input leakage current I I power-off leakage OFF current I power-up/power-down O(pu/pd) output current I OFF-state output OZ current I output leakage current HIGH-state output current O I supply current CC I additional supply CC current C input capacitance ...

Page 6

... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure Symbol Parameter Conditions t OFF-state to LOW OE to Qn; see PZL propagation delay t HIGH to OFF-state OE to Qn; see PHZ propagation delay t LOW to OFF-state OE to Qn; see PLZ propagation delay t set-up time HIGH Dn to CP; see ...

Page 7

... NXP Semiconductors Dn input CP input The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 7. Set-up and hold times data output (Dn) to clock (CP) OE input Qn output Qn output and V are typical output voltage levels that occur with the output load ...

Page 8

... NXP Semiconductors negative V M pulse positive V M pulse Input pulse definition Test data is given in Table R = Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times ...

Page 9

... NXP Semiconductors 12. Package outline DIP20: plastic dual in-line package; 20 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 10

... NXP Semiconductors SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 11

... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT339-1 Fig 12 ...

Page 12

... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 13

... Document ID Release date 74ABT374A v.2 20121218 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 74ABT374A v.1 19950906 74ABT374A Product data sheet Octal D-type flip-flop ...

Page 14

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 15

... Octal D-type flip-flop; positive-edge trigger; 3-state NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 16

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Abbreviations ...

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