89H32NT24BG2ZCHLGI IDT, 89H32NT24BG2ZCHLGI Datasheet - Page 19

• Manufacturer Part Number: 89H32NT24BG2ZCHLGI
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: IDT

Specifications of 89H32NT24BG2ZCHLGI

• Rohs: yes
• Part # Aliases: IDT89H32NT24BG2ZCHLGI

IDT 89HPES32NT24AG2 Data Sheet
T
T
DATA
T
T
T
T
PCIe Receive
UI
T
T
MAX JITTER
T
T
T
T
T
TX-IDLE-SET-TO-IDLE
TX-IDLE-TO-DIFF-
TX-SKEW
MIN-PULSED
TX-HF-DJ-DD
RF-MISMATCH
RX-EYE (with jitter)
RX-EYE-MEDIUM TO
RX-SKEW
RX-HF-RMS
RX-HF-DJ-DD
RX-LF-RMS
RX-MIN-PULSE
1.
Parameter
Minimum, Typical, and Maximum values meet the requirements under PCI Express Base Specification 2.1.
Maximum time to transition to a valid Idle after sending
an Idle ordered set
Maximum time to transition from valid idle to diff data
Transmitter data skew between any 2 lanes
Minimum Instantaneous Lone Pulse Width
Transmitter Deterministic Jitter > 1.5MHz Bandwidth
Rise/Fall Time Differential Mismatch
Unit Interval
Minimum Receiver Eye Width (jitter tolerance)
Max time between jitter median & max deviation
Lane to lane input skew
1.5 — 100 MHz RMS jitter (common clock)
Maximum tolerable DJ by the receiver (common clock)
10 KHz to 1.5 MHz RMS jitter (common clock)
Minimum receiver instantaneous eye width
GPIO (asynchronous input)
GPIO
GPIO[8:0]
1.
are asynchronous.
2.
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they
The values for this symbol were determined by calculation, not by testing.
Signal
1
Description
EXTCLK
Table 12 PCIe AC Timing Characteristics (Part 2 of 2)
Symbol
Tpw_13b
Table 13 GPIO AC Timing Characteristics
Figure 4 GPIO AC Timing Waveform
2
Reference
Edge
None
19 of 38
399.88
Min
Tpw_13b
0.4
Min
50
1
Gen 1
Typ
Max Unit
400
NA
NA
NA
NA
NA
NA
NA
—
1
Max
400.12
ns
1.3
0.3
20
8
8
1
Reference
See Figure 4.
Min
199.94
Diagram
Timing
0.9
0.4
0.6
1
Gen 2
Typ
1
Max
200.06
0.15
1.3
0.1
3.4
4.2
88
8
8
8
1
March 14, 2012
Units
ps
ns
ns
ns
UI
UI
UI
ps
UI
UI
ns
ps
ps
UI