MAX1965TEEP Maxim Integrated, MAX1965TEEP Datasheet - Page 23

• Manufacturer Part Number: MAX1965TEEP
• Description: Current & Power Monitors & Regulators
• Manufacturer: Maxim Integrated

current and load resistance, the total DC loop gain
(A
where V
base-to-emitter resistor (R
cally 220Ω, providing approximately 3.2mA of bias cur-
rent.
The output capacitor creates the dominant pole.
However, the pass transistor’s input capacitance creates
a second pole in the system. Additionally, the output
capacitor’s ESR generate a zero, which may be used to
cancel the second pole if necessary. Therefore, in order
to achieve stable operation, use the following equations
to verify that the linear regulator is properly compensat-
ed:
1) First, determine the dominant pole set by the linear
2) Next, determine the second pole set by the base-to-
3) A third pole is set by the linear regulator’s feedback
4) If the second and third pole occur well after unity-
However, if the ESR zero occurs before unity-gain
crossover, cancel the zero with f
circuit components such that:
V(LDO)
regulator’s output capacitor and the load resistor:
unity-gain crossover = A
emitter capacitance (including the transistor’s input
capacitance), the transistor’s input resistance, and
the base-to-emitter pullup resistor:
resistance and the capacitance between FB_ and
GND (including 20pF stray capacitance).
gain crossover, the linear regulator will remain stable:
ƒ
POLE CLDO
T
) is approximately:
A
is 26mV, and I
ƒ
(
POLE CBE
V LDO
(
ƒ
POLE(FB)
ƒ
(
POLE FB
2
)
)
ƒ
=
______________________________________________________________________________________
≈
POLE(CLDO)
2



)
π
(
5 5
V
=
=
C
.
T
LDO LOAD
2
and ƒ
)
R
BIAS

 +

2
Tracking/Sequencing Triple/Quintuple
π
=
BE LOAD
BE




π
C
1
1
V(LDO)
C
2
R
BE
I
). This bias resistor is typi-
π
BE BE T FE



POLE(CBE) >
is the current through the
C
I
A
(
BIAS FE
FB
R
R
I
V(LDO)
LOAD
BE
POLE(FB)
1
(
1
ƒ
R R
+
h
=
POLE(CLDO)
V h
1 2
R
V h
2
T FE
IN BJT
I
π
LOAD MAX



(
)
C




V
LDO LDO
REF
by changing
)
(
)
V
)
Power-Supply Controllers
Do not use output capacitors with more than 200mΩ of
ESR. Typically, more output capacitance provides the
best solution, since this also reduces the output voltage
drop immediately after a load transient.
Connect at least 1µF capacitor between the linear regu-
lator’s output and ground, as close to the MAX1964/
MAX1965 and external pass transistors as possible.
Depending on the selected pass transistor, larger
capacitor values may be required for stability (see
Stability Requirements). Furthermore, the output capac-
itor’s equivalent series resistance (ESR) affects stability,
providing a zero that may be necessary to cancel the
second pole. Use output capacitors with an ESR less
than 200mΩ to ensure stability and optimum transient
response.
Once the minimum capacitor value for stability is deter-
mined, verify that the linear regulator’s output does not
contain excessive noise. Although adequate for stabili-
ty, small capacitor values may provide too much band-
width, making the linear regulator sensitive to noise.
Larger capacitor values reduce the bandwidth, thereby
reducing the regulator’s noise sensitivity.
For the negative linear regulator, if noise on the ground
reference causes the design to be marginally stable,
bypass the negative output back to its reference volt-
age (V
ential noise on the output.
The high-impedance base driver is susceptible to sys-
tem noise, especially when the linear regulator is lightly
loaded. Capacitively coupled switching noise or induc-
tively coupled EMI onto the base drive causes fluctua-
tions in the base current, which appear as noise on the
linear regulator’s output. Keep the base-drive traces
away from the step-down converter and as short as
possible to minimize noise coupling. Resistors in series
with the gate drivers (DH and DL) reduce the LX
switching noise generated by the step-down converter
(Figure 5). Additionally, a bypass capacitor may be
placed across the base-to-emitter resistor (Figure 7).
This bypass capacitor, in addition to the transistor’s
input capacitance, could bring in a second pole that
will destabilize the linear regulator (see Stability
Requirements). Therefore, the stability requirements
determine the maximum base-to-emitter capacitance:
REF
, Figure 7). This technique reduces the differ-
ƒ
POLE FB
Linear Regulator Output Capacitors
(
)
Base-Drive Noise Reduction
≈
π
C
OUT ESR
1
R
23