MAX1808EUB+ Maxim Integrated, MAX1808EUB+ Datasheet - Page 17

• Manufacturer Part Number: MAX1808EUB+
• Description: Current & Power Monitors & Regulators
• Manufacturer: Maxim Integrated

The gain of the error amplifier (GAIN
quencies is:
The total loop gain as the product of the modulator gain
and the error amplifier gain at f
So:
Solving for C
3) Use the second pole (f
When using a ceramic capacitor, the capacitor ESR
zero f
switching frequency, f
case, place the frequency of the second pole (f
enough to not significantly erode the phase margin at
the crossover frequency. For example, set f
so that the contribution to phase loss at the crossover
frequency f
Once f
4) Place the second zero (f
Maxim Integrated
f
loop gain does not flatten out soon after the 0dB
crossover, and maintains a -20dB/decade slope up
to 1/2 of the switching frequency. This is likely to
occur if the output capacitor is a low-ESR tantalum.
Set f
whichever is lower, and calculate R
lowing equation:
O
< f
ZO
P2
Low-Cost, Small, 4.5V to 28V Wide Operating
P2
C
ZO
is known, calculate R
is likely to be located even above 1/2 the
Range, DC-DC Synchronous Buck Controller
I
= f
V
O
=
RAMP
V
I
< f
:
ZO
is only about 11°:
IN
V
GAIN
RAMP
.
SW
GAIN
R
×
1
/2. The frequency response of the
EA
R
(
=
2
×
I
MOD
f
π
=
P2
2
(
= 2π x f
2π
PO
π
×
2
= 5 x f
π
×
f
O
V
×
P2
×
f
IN
< f
×
)
Z
1
2
f
GAIN
O
) to cancel f
2
f
P
1
Z2
×
×
O
O
2
×
×
O
I:
R
PO
C
1
) at 0.2 x f
L
×
C
x C
F
< f
is 1.
OUT
EA
OUT
I
C
−
I
1
SW
R
EA
= 1
x R
I
×
×
/2 < f
) in midband fre-
L
C
1
OUT
F
ZO
OUT
using the fol-
O
P2
when f
ZO
)
or at f
at 5 x f
. In this
P2
) high
PO
PO
O
<
,
5) Place the third pole (f
6) Calculate R
The MAX15026 step-down controller drives two external
logic-level n-channel MOSFETs. The key selection
parameters to choose these MOSFETs include:
• On-Resistance (R
• Maximum Drain-to-Source Voltage (V
• Minimum Threshold Voltage (V
• Total Gate Charge (Q
• Reverse Transfer Capacitance (C
• Power Dissipation
The two n-channel MOSFETs must be a logic-level type
with guaranteed on-resistance specifications at V
4.5V. For maximum efficiency, choose a high-side
MOSFET that has conduction losses equal to the
switching losses at the typical input voltage. Ensure
that the conduction losses at minimum input voltage do
not exceed the MOSFET package thermal limits, or vio-
late the overall thermal budget. Also, ensure that the
conduction losses plus switching losses at the maxi-
mum input voltage do not exceed package ratings or
violate the overall thermal budget. Ensure that the DL
gate driver can drive the low-side MOSFET. In particu-
lar, check that the dv/dt caused by the high-side
MOSFET turning on does not pull up the low-side
MOSFET gate through the drain-to-gate capacitance
of the low-side MOSFET, which is the most frequent
cause of cross-conduction problems.
Check power dissipation when using the internal linear
regulator to power the gate drivers. Select MOSFETs
with low gate charge so that V
vers without overheating the device.
where Q
two external MOSFETs.
quency and calculate C
G_TOTAL
C
P
CF
DRIVE
2
=
as:
(
R
is the sum of the gate charges of the
2
2
= V
DS(ON)
π
=
×
CC
V
0 5
G
OUT
.
)
x Q
)
P3
×
V
CF
FB
f
SW
−
) at 1/2 the switching fre-
MAX15026
:
C
G_TOTAL
V
F
FB
CC
MOSFET Selection
×
TH(MIN)
R
×
F
RSS
can power both dri-
R
×
1
C
DS(MAX)
)
x f
)
F
SW
)
−
1
)
GS
17
=