MAX1885EUP-T Maxim Integrated, MAX1885EUP-T Datasheet - Page 32

• Manufacturer Part Number: MAX1885EUP-T
• Description: LCD Drivers Quad-Output TFT LCD DC-DC Converter with Buffer
• Manufacturer: Maxim Integrated

Specifications of MAX1885EUP-T

• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: TSSOP-20
• Mounting Style: SMD/SMT

Quad-Output TFT LCD DC/DC
Converters with Buffer
MAX1778/MAX1880–MAX1885
32
3) Locate all feedback resistive-dividers as close as
4) When using multilayer boards, separate the top sig-
Figure 8. 5V Input Monitor Application
layer boards, the top layer should contain the boost
regulator and charge-pump power ground plane,
and the inner layer should contain the analog
ground plane and power-ground plane/path for the
VCOM buffer and LDO. Connect all three ground
planes together at one place near the PGND pin.
possible to their respective feedback pins. The volt-
age-divider’s center trace should be kept short.
Avoid running any feedback trace near the LX
switching node or the charge-pump drivers. The
resistive-dividers’ ground connections should be to
analog ground (GND).
nal layer and bottom signal layer with a ground
plane between to eliminate capacitive coupling
V
LDO
= 3.3V
1µF
LDO
V
C6
IN
INPUT
= 5V
0.01µF
10kΩ
C7
R8
(2) 4.7µF
V
NEGATIVE
NEG
16.4kΩ
C
IN
= -8V
TO LOGIC
R7
Q1
1.0µF
100kΩ
C3
R
RDY
C
LDOOUT
C6
0.01µF
4.7µF
0.22µF
C
REF
0.22µF
316kΩ
R5
C1
49.9kΩ
1.5kΩ
R8
R6
0.1µF
C2
LDOOUT
SUPL
FBL
DRVN
FBN
IN
SHDN
RDY
REF
INTG
PGND
MAX1778
10µH
L1
5) Keep the charge-pump circuitry as close as possi-
6) To maximize output power and efficiency and mini-
Refer to the MAX1778/MAX1880–MAX1885 evaluation
kit for an example of proper board layout.
BUFOUT
FLTSET
SUPB
SUPN
SUPP
DRVP
TGND
BUF-
BUF+
GND
FBP
between fast-charging nodes on the top layer and
high-impedance nodes on the bottom layer. The
fast-charging nodes, such as the LX and charge-
pump driver nodes, should not have any other
traces or ground planes near by.
ble to the IC, using wide traces and avoiding vias
when possible. Place 0.1µF ceramic bypass
capacitors near the charge-pump input pins (SUPP
and SUPN) to the PGND pin.
mize output ripple voltage, use extra-wide, power-
ground traces, and solder the IC’s power-ground
pin directly to it.
LX
FB
0.1µF
C4
86.6kΩ
R4
49.9kΩ
10kΩ
R1
R2
R10
100kΩ
C
1.0µF
BUF
750kΩ
R3
R
4.7kΩ
C
COMP
470pF
COMP
30kΩ
R9
BUFFER OUTPUT
V
BUFOUT
= V
SUPB
C5
1.0µF
C
(2) 10µF
REF
OUT
/2
Maxim Integrated
POSITIVE
V
MAIN
V
MAIN
POS
= 20V
= 12V