93LC86C-I/SN Microchip Technology, 93LC86C-I/SN Datasheet - Page 8

• Manufacturer Part Number: 93LC86C-I/SN
• Description: IC EEPROM 16KBIT 3MHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 93LC86C-I/SN

• Memory Size: 16K (2K x 8 or 1K x 16)
• Package / Case: 8-SOIC (3.9mm Width)
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 3MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 2 K x 8 or 1 K x 16
• Interface Type: Microwire
• Maximum Clock Frequency: 3 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
2.6
The 93XX86A/B/C powers up in the Erase/Write
Disable (EWDS) state. All programming modes must be
preceded by an Erase/Write Enable (EWEN) instruction.
FIGURE 2-3:
FIGURE 2-4:
2.7
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (If ORG pin is low or A-Version
devices) or 16-bit (If ORG pin is high or B-version
devices) output string.
FIGURE 2-5:
DS21797J-page 8
CLK
CLK
CS
DO
CS
DI
CLK
DI
CS
DI
Erase/Write Disable and Enable
(EWDS/EWEN)
Read
High-Z
1
1
1
EWDS TIMING
EWEN TIMING
READ TIMING
1
0
0
0
0
0
A
N
0
1
•••
0
A0
1
0
Dx
x
x
•••
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or V
To protect against accidental data disturbance, the
EWDS instruction can be used to disable all Erase/Write
functions
operations. Execution of a READ instruction is
independent of both the EWEN and EWDS instructions.
The output data bits will toggle on the rising edge of the
CLK and are stable after the specified time delay (T
Sequential read is possible when CS is held high. The
memory data will automatically cycle to the next register
and output sequentially.
•••
•••
D0
CC
is removed from the device.
Dx
and
x
x
•••
T
T
CSL
CSL
should
D0
© 2008 Microchip Technology Inc.
Dx
follow
•••
all
D0
programming
PD
).