25LC256-I/ST Microchip Technology, 25LC256-I/ST Datasheet - Page 10

• Manufacturer Part Number: 25LC256-I/ST
• Description: IC EEPROM 256KBIT 10MHZ 8TSSOP
• Manufacturer: Microchip Technology

Specifications of 25LC256-I/ST

• Memory Size: 256K (32K x 8)
• Package / Case: 8-TSSOP
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 32 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 10 MHz
• Access Time: 50 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

25AA256/25LC256
2.5
The Read Status Register instruction (RDSR) provides
access to the Status register. The Status register may
be read at any time, even during a write cycle. The
Status register is formatted as follows:
TABLE 2-2:
The Write-In-Process (WIP) bit indicates whether the
25XX256 is busy with a write operation. When set to a
‘
in progress. This bit is read-only.
FIGURE 2-6:
DS21822C-page 10
1
W/R = writable/readable. R = read-only.
WPEN
SCK
’, a write is in progress, when set to a ‘
W/R
CS
SO
7
SI
Read Status Register Instruction
(RDSR)
X
6
–
0
5
X
–
0
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
STATUS REGISTER
4
–
X
0
1
W/R
high-impedance
BP1
3
0
instruction
2
W/R
BP0
0
2
3
0
WEL
0
4
R
1
’, no write is
1
5
WIP
R
0
Preliminary
0
6
1
7
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘
‘
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the Status register. These commands are shown in
Figure 2-4 and Figure 2-5.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile, and are shown in Table 2-3.
See Figure 2-6 for the RDSR timing sequence.
7
0
8
’, the latch prohibits writes to the array. The state of
1
’, the latch allows writes to the array, when set to a
6
9
data from Status register
10
5
11
4
 2003 Microchip Technology Inc.
12
3
13
2
14
1
15
0