25LC256-I/ST Microchip Technology, 25LC256-I/ST Datasheet - Page 11

• Manufacturer Part Number: 25LC256-I/ST
• Description: IC EEPROM 256KBIT 10MHZ 8TSSOP
• Manufacturer: Microchip Technology

Specifications of 25LC256-I/ST

• Memory Size: 256K (32K x 8)
• Package / Case: 8-TSSOP
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 32 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 10 MHz
• Access Time: 50 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

2.6
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the Status register
as shown in Table 2-2. The user is able to select one of
four levels of protection for the array by writing to the
appropriate bits in the Status register. The array is
divided up into four segments. The user has the ability
to write-protect none, one, two, or all four of the
segments of the array. The partitioning is controlled as
shown in Table 2-3.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the Status register control the
programmable hardware write-protect feature. Hard-
ware write protection is enabled when WP pin is low
and the WPEN bit is high. Hardware write protection is
disabled when either the WP pin is high or the WPEN
bit is low. When the chip is hardware write-protected,
only writes to nonvolatile bits in the Status register are
disabled. See Table 2-4 for a matrix of functionality on
the WPEN bit.
FIGURE 2-7:
 2003 Microchip Technology Inc.
SCK
Note:
CS
SO
SI
Write Status Register Instruction
(WRSR)
An internal write cycle (T
0
0
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
0
1
0
2
instruction
0
3
WC
) is initiated on the rising edge of CS after a valid write Status Register sequence.
0
4
0
5
high-impedance
Preliminary
0
6
1
7
See Figure 2-7 for the WRSR timing sequence.
TABLE 2-3:
7
8
BP1
0
0
1
1
6
25AA256/25LC256
9
data to Status register
10
5
11
4
ARRAY PROTECTION
BP0
0
1
0
1
12
3
13
2
Array Addresses
Write-Protected
(6000h - 7FFFh)
(4000h - 7FFFh)
(0000h - 7FFFh)
upper 1/4
14
upper 1/2
1
DS21822C-page 11
none
all
15
0