E909.05A61DC ELMOS Semiconductor, E909.05A61DC Datasheet - Page 53

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E909.05A61DC

Manufacturer Part Number
E909.05A61DC
Description
Processors - Application Specialized Halios multipurpose sensor IC
Manufacturer
ELMOS Semiconductor
Datasheet

Specifications of E909.05A61DC

Rohs
yes
Processor Series
EL16
Data Bus Width
16 bit
Maximum Clock Frequency
8 MHz
Data Ram Size
3 kB
Operating Supply Voltage
2.25 V to 2.75 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-32
Interface Type
I2C, SPI
Memory Type
Flash, SRAM
Minimum Operating Temperature
- 40 C
Number Of Timers
2
PRELIMINARY INFORMATION AUG 02, 2011
The hardware multiplier is a peripheral and is not part of the EL16 CPU. This means, its activities do not inter-
fere with the CPU activities. The multiplier registers are peripheral registers that are loaded and read with
CPU instructions.
The hardware multiplier supports:
The hardware multiplier supports unsigned multiply, signed multiply, unsigned multiply accumulate, and
signed multiply accumulate operations. The type of operation is selected by the address the first operand is
written to. The hardware multiplier has two 16-bit operand registers, OP1 and OP2, and three result registers,
SumLo, SumHi, and SumExt. SumLo stores the low word of the result, SumHi stores the high word of the
result, and SumExt stores information about the result.
Table 6.12.1.1: Multiplier Module Registers
Register MPY (0x10)
Table 6.12.1.2: MPY
Register MPYS (0x12)
This document contains information on a pre-production product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
ELMOS Semiconductor AG
Bit
Reset value
Internal access
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
Bit
Reset value
Internal access
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
6.12 Multiplier Module
6.12.1 Module Registers
address offset
HALIOS® MULTI-PURPOSE OPTICAL SENSOR WITH HIGH LIGHT IMMUNITY
0x1A
0x1C
0x1E
0x10
0x12
0x14
0x16
0x18
Unsigned multiply
Signed multiply
Unsigned multiply accumulate
Signed multiply accumulate
16 x 16 bits, 16 x 8 bits, 8 x 16 bits, 8 x 8 bits
CPU is halted until result is valid (1 clock cycle)
15
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15:0 : Operand 1
unsigned multiply
15
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15:0 : Operand 1
signed multiply
reset value
14
0
14
0
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
13
0
13
0
12
0
12
0
MPY (operand 1)
MPYS (operand 1)
MAC (operand 1)
MACS (operand 1)
operand 2
SumLo
SumHi
SumExt
11
0
11
0
Data Sheet 53 / 67
10
0
10
0
9
0
9
0
8
0
8
0
register name
7
0
7
0
6
0
6
0
5
0
5
0
4
0
4
0
QM-No.: 25DS0014E.00
3
0
3
0
2
0
2
0
E909.05
1
0
1
0
size
0
0
0
0
16
16
16
16
16
16
16
16

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