E909.06A61DC ELMOS Semiconductor, E909.06A61DC Datasheet - Page 46

• Manufacturer Part Number: E909.06A61DC
• Description: Processors - Application Specialized Halios multipurpose sensor IC - Auto
• Manufacturer: ELMOS Semiconductor

Specifications of E909.06A61DC

• Rohs: yes
• Processor Series: EL16
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 8 MHz
• Data Ram Size: 3 kB
• Operating Supply Voltage: 2.25 V to 2.75 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Interface Type: I2C, SPI
• Memory Type: Flash, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

5.11.7 I²C Wake-up Detection
The I²C interface can be used to wake up the IC from any system state. In system state "off" the interface has to
be configured to wake the CPU Therefore the 'wake-up mode enable bit' has to be set (defined in control register)
before setting the IC to "off-mode".
It is only possible to set the 'wake-up mode enable bit' if the I²C Master has closed the communication on the
bus, so the application software has to poll the bit 'wake-up mode enable' (defined in status register) after it was
set to make sure the bus is in idle state and the IC can be set to "off-mode".
After a new addressing of the slave on the bus the system will wake up from "off-mode" and the "I²C wake-up
event" interrupt is active as long as the 'wake-up mode enable bit' is set back to zero (defined in control register).
While the wake-up process the interface will force the Master into a wait state by holding the SCL line low. The
application software has to clear the 'wake-up mode enable bit' (defined in control register) to release the SCL
line in order to continue the communication.
5.12 Interrupt Control Module
5.12.1 Interrupt Control Module Structure
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Figure 15: Interrupt control circuit
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
PRODUCTION DATA - NOV 16, 2011
ELMOS Semiconductor AG
Interrupt pending bit flip-flops (request hold elements) are located inside asserting modules
Interrupt vector support for more simple and faster interrupt entry
Fast vector based interrupt enable / disable
Nested interrupt support
FLASH based main interrupt vector
Main interrupt enable MIE for easy cli() and sei() implementation
N is the number of interrupt vectors
and GPIO
Interrupt
Sources
Module
Interrupt
Status
N
Interrupt
Mask
N
N
AND
Interrupt
Masked
Status
Data Sheet
46/71
N
Vector
Interrupt
Logic
Vector
N
OR
MIE
QM-No.: 25DS0049E.02
1
E909.06
Interrupt
to CPU