MCIMX6U7CVM08AB Freescale Semiconductor, MCIMX6U7CVM08AB Datasheet - Page 75

• Manufacturer Part Number: MCIMX6U7CVM08AB
• Description: Processors - Application Specialized i.MX6 DualLite
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6U7CVM08AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Data Ram Size: 128 KB
• Maximum Operating Temperature: + 105
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-624
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

For DDR Toggle mode,
value of tDQSQ is 1.4 ns(max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI will sample DQ[7:0] at
both rising and falling edge of an delayed DQS signal, which is provided by an internal DPLL. The delay
value of this register can be controlled by GPMI register
GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX
6Solo/6DualLite reference manual). Generally, the typical delay value is equal to 0x7 which means 1/4
clock cycle delay expected. But if the board delay is big enough and cannot be ignored, the delay value
should be made larger to compensate the board delay.
4.11
The following subsections provide information on external peripheral interfaces.
4.11.1
The AUDMUX provides a programmable interconnect logic for voice, audio, and data routing between
internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of
AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI
electrical specifications found within this document.
4.11.2
This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing
parameters for master and slave modes.
Freescale Semiconductor
NF23
NF24
NF25
NF26
ID
External Peripheral Interface Parameters
AUDMUX Timing Parameters
ECSPI Timing Parameters
preamble delay
postamble delay
CLE and ALE setup time
CLE and ALE hold time
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
Table 49. Samsung Toggle Mode Timing Parameters (continued)
Parameter
Figure 35
shows the timing diagram of DQS/DQ read valid window. The typical
Symbol
tPOST
tCALS
tCALH
tPRE
(PRE_DELAY+1) x tCK
POST_DELAY x tCK
0.5 x tCK
0.5 x tCK
Min.
T = GPMI Clock Cycle
Timing
Max.
—
—
—
—
Electrical Characteristics
Unit
ns
ns
ns
ns
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