70T3539MS133BC IDT, 70T3539MS133BC Datasheet - Page 13

• Manufacturer Part Number: 70T3539MS133BC
• Description: SRAM 512K X 36 STD-PWR, 2.5V DUAL PORT RAM
• Manufacturer: IDT
• Series: IDT70T3539Mr
• Type: Dual Port RAMr

Specifications of 70T3539MS133BC

• Memory Size: 18 Mbit
• Organization: 512 K x 36
• Access Time: 4.2 ns
• Supply Voltage - Max: 2.6 V
• Supply Voltage - Min: 2.4 V
• Maximum Operating Current: 740 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-256
• Interface: LVTTL
• Maximum Clock Frequency: 133 MHz
• Memory Type: Synchronous
• Part # Aliases: IDT70T3539MS133BC

Timing Waveform of Left Port Write to Pipelined Right Port Read
NOTES:
1. CE
2. OE = V
3. If t
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read
NOTES:
1. CE
2. OE = V
3. If t
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
ADDRESS
ADDRESS
t
will be t
ADDRESS
ADDRESS
t
be t
DATA
CO
CO
DATA
DATA
CO
CO
0
0
DATA
, BE
+ 2 t
, BEn, and ADS = V
+ t
CO
CLK
CLK
R/W
R/W
< minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
< minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
OUT"B"
CYC
CLK
R/W
CLK
R/W
+ t
IL
IL
CO
OUT "B"
IN"A"
n
CYC2
, and ADS = V
"A"
"A"
"B"
"B"
"B"
for Port "B", which is being read from. OE = V
IN "A"
for the Right Port, which is being read from. OE = V
CD1
"A
+ t
+ t
"
"A"
"A"
"A"
"B"
"B"
"B"
).
CYC2
CD1
+ t
CD2
). If t
+ t
). If t
CD2
CO
IL
IL
CO
).
> minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
; CE
t
MATCH
t
; CE
t
SW
SD
VALID
SA
> minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
t
t
MATCH
MATCH
VALID
1
t
t
SW
t
SA
1
SW
SA
SD
, CNTEN, and REPEAT = V
, CNTEN, and REPEAT = V
t
t
t
HW
HA
HD
MATCH
t
t
SW
SA
t
t
HW
HA
t
t
t
HW
HA
HD
t
DC
t
t
t
CO
HW
HA
(3)
t
CO
(3)
t
CD1
IH
IH
for Port "A", which is being written to.
IH
.
.
IH
for the Left Port, which is being written to.
MATCH
NO
6.42
13
t
CD2
VALID
MATCH
NO
MATCH
NO
Industrial and Commercial Temperature Ranges
VALID
MATCH
t
DC
NO
t
CD1
(1,2,4)
t
DC
VALID
5678 drw 09
5678 drw 10
(1,2,4)
,
,