70T3539MS133BC IDT, 70T3539MS133BC Datasheet - Page 5

• Manufacturer Part Number: 70T3539MS133BC
• Description: SRAM 512K X 36 STD-PWR, 2.5V DUAL PORT RAM
• Manufacturer: IDT
• Series: IDT70T3539Mr
• Type: Dual Port RAMr

Specifications of 70T3539MS133BC

• Memory Size: 18 Mbit
• Organization: 512 K x 36
• Access Time: 4.2 ns
• Supply Voltage - Max: 2.6 V
• Supply Voltage - Min: 2.4 V
• Maximum Operating Current: 740 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-256
• Interface: LVTTL
• Maximum Clock Frequency: 133 MHz
• Memory Type: Synchronous
• Part # Aliases: IDT70T3539MS133BC

Truth Table I—Read/Write and Enable Control
NOTES:
1. "H" = V
2. ADS, CNTEN, REPEAT = X.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table II—Address Counter Control
NOTES:
1. "H" = V
2. Read and write operations are controlled by the appropriate setting of R/W, CE
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE
5. The address counter advances if CNTEN = V
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
OE
Address
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
X
X
X
X
X
X
X
X
X
X
H
X
L
L
L
L
L
L
L
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
An
X
X
X
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
IH,
IH,
X
"L" = V
"L" = V
Previous
Address
Internal
An + 1
CE
An
H
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
IL,
IL,
0
"X" = Don't Care.
"X" = Don't Care.
CE
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
L
Address
1
Internal
An + 1
An + 1
Used
An
An
BE
X
X
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
3
CLK
BE
X
X
H
H
H
H
H
H
H
H
H
X
X
↑
↑
↑
↑
L
L
L
L
L
L
2
IL
BE
X
X
H
H
H
H
H
H
H
H
H
X
X
ADS
L
L
L
L
L
L
on the rising edge of CLK, regardless of all other memory control signals including CE
X
1
L
H
H
(4)
BE
X
X
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
CNTEN
0
X
L
H
X
(5)
R/W
X
X
X
X
X
L
L
L
L
L
L
L
H
H
H
H
H
H
H
REPEAT
L
ZZ
H
H
H
(4)
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
(6)
6.42
5
I/O
Byte 3
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
0
D
D
D
, CE
D
D
D
D
D
D
D
OUT
OUT
OUT
I/O
I/O
27-35
I/O
IN
IN
IN
I/O
I/O
(n+1)
(n+1)
0
1
, CE
(3)
(n)
(n)
, BEn and OE.
(1,2)
1
and BEn
I/O
Byte 2
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
External Address Used
Counter Enabled—Internal Address generation
External Address Blocked—Counter disabled (An + 1 reused)
Counter Set to last valid ADS load
D
D
D
D
D
D
OUT
OUT
OUT
18-26
IN
IN
IN
(1,2,3,4)
Industrial and Commercial Temperature Ranges
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Byte 1
I/O
D
D
D
D
D
D
OUT
OUT
OUT
9-17
IN
IN
IN
Byte 0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
I/O
D
D
D
D
D
D
OUT
OUT
OUT
IN
IN
IN
0-8
MODE
Deselected–Power Down
Deselected–Power Down
Read Byte 0 Only
Read Byte 1 Only
Read Byte 2 Only
Read Byte 3 Only
Read Lower 2 Bytes Only
Read Upper 2 Bytes Only
Read All Bytes
Outputs Disabled
Sleep Mode
All Bytes Deselected
Write to Byte 0 Only
Write to Byte 1 Only
Write to Byte 2 Only
Write to Byte 3 Only
Write to Lower 2 Bytes Only
Write to Upper 2 bytes Only
Write to All Bytes
0
, CE
1
MODE
, BEn.
5678 tbl 02
5678 tbl 03