70V3319S133BF IDT, 70V3319S133BF Datasheet
70V3319S133BF
Specifications of 70V3319S133BF
Related parts for 70V3319S133BF
70V3319S133BF Summary of contents
Page 1
... Dual chip enables allow for depth expansion without additional logic Full synchronous operation on both ports – 6ns cycle time, 166MHz operation (6Gbps bandwidth) – Fast 3.6ns clock to data out – 1.7ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 166MHz – ...
Page 2
... IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Description: The IDT70V3319/ high-speed 256/128K x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times ...
Page 3
... TCK NC A 17R NOTES for IDT70V3399 All V pins must be connected to 3.3V power supply All V pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V DDQ set to V (0V All V pins must be connected to ground supply. ...
Page 4
... A 36 16R A 37 15R A 38 14R NOTES for IDT70V3399 All V pins must be connected to 3.3V power supply All V pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V DDQ 4. All V pins must be connected to ground supply Package body is approximately 14mm x 20mm x 1.4mm. ...
Page 5
... NOTES: (2, for IDT70V3399. DDQX OPT , and (2) applying inputs on the I/Os and controls for that port. 3. OPT selects the operating voltage levels for the I/Os and controls on that port OPT is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V ...
Page 6
... IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Truth Table I—Read/Write and Enable Control OE CE CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ NOTES: 1. "H" "L" " ...
Page 7
... IL DDQX at 3.3V DDQ Parameter Min. Typ. 3.15 3.3 (3) 3.15 3 ____ 2.0 V DDQ (3) (3) 2.0 ____ V DDQ (1) -0.3 ____ -1.5V for pulse width less than 10ns is allowed. IL > + 150mV. DDQ (3.3V), and V IH DDQX Max. Unit 3. (2) + 100mV V (2) + 100mV V 0.7 V 5623 tbl 05a Max. Unit 3. ...
Page 8
... IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM (1) Capacitance (T = +25° 1.0MH A Symbol Parameter Conditions C Input Capacitance IN (3) C Output Capacitance OUT NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from from ...
Page 9
... IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter CE and CE I Dynamic Operating DD L Current (Both Outputs Disabled, Ports Active MAX Standby Current SB1 L (Both Ports - TTL Outputs Disabled, ...
Page 10
... IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM AC Test Conditions (V Input Pulse Levels (Address & Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 50Ω DATA OUT Figure 1. AC Output Test load ∆tCD ...
Page 11
... IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) Symbol t Clock Cycle Time (Flow-Through) CYC1 (1) t Clock Cycle Time (Pipelined) CYC2 t Clock High Time (Flow-Through) CH1 t Clock Low Time (Flow-Through) ...
Page 12
... IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Timing Waveform of Read Cycle for Pipelined Operation (2) (FT/PIPE = CH2 CLK UB (4) ADDRESS An (1 Latency) DATA OUT (1) OE Timing Waveform of Read Cycle for Flow-through Output ...
Page 13
... ADDRESS 0 (B2) CE 0(B2 DATA OUT(B2) NOTES Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3319/99 for this waveform, and are setup for depth expansion in this example. ADDRESS 2. UB, LB, OE, and ADS = 1(B1) 1(B2 ...
Page 14
... IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Timing Waveform of Left Port Write to Pipelined Right Port Read CLK "A" R/W "A" ADDRESS "A" MATCH DATA VALID IN"A" CLK "B" R/W "B" ...
Page 15
... IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Timing Waveform of Pipelined Read-to-Write-to-Read (2) ( CYC2 t t CH2 CLK UB (3) An ADDRESS DATA IN (1) DATA OUT READ NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. ...
Page 16
... IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Timing Waveform of Flow-Through Read-to-Write-to-Read ( CYC1 t t CH1 CLK UB (3) An ADDRESS DATA IN t CD1 (1) DATA OUT READ Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled) ...
Page 17
... IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Timing Waveform of Pipelined Read with Address Counter Advance t CYC2 t t CH2 CL2 CLK ADDRESS SAD HAD ADS CNTEN ( DATA OUT READ EXTERNAL ADDRESS Timing Waveform of Flow-Through Read with Address Counter Advance ...
Page 18
... IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Timing Waveform of Write with Address Counter Advance (Flow-through or Pipelined Inputs) t CYC2 t CH2 CLK ADDRESS An (3) INTERNAL An ADDRESS t t SAD HAD ADS CNTEN DATA IN WRITE EXTERNAL ADDRESS Timing Waveform of Counter Repeat ...
Page 19
... Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The IDT70V3319/99 can also be used in applications requiring expanded width, as indicated in Figure 4. Through combining the control signals, the devices can be grouped as necessary to accommodate applications needing 36-bits or wider. ...
Page 20
... IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM JTAG Timing Specifications t JF TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO TRST t JRST NOTES: 1. Device inputs = All device inputs except TDI, TMS, and TRST. 2. Device outputs = All device outputs except TDO. JTAG AC Electrical ...
Page 21
... Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, and TRST. 3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com contacting your local IDT sales representative. Industrial and Commercial Temperature Ranges ...
Page 22
... Ordering Information XXXXX A 999 A Device Power Speed Package Type NOTE: 1. Green parts available. For specific speeds, packages and powers contact your local sales office. IDT Clock Solution for IDT70V3319/99 Dual-Port Dual-Port I/O Specitications IDT Dual-Port Part Number Voltage 70V3319/99 3.3/2 Process/ Temperature Range ...
Page 23
... Page 22 Removed "IDT" from orderable part number CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc. value in AC Electrical Characteristics, please refer to Errata #SMEN-01-05 logo with ® logo TM and added T ...