70V3319S133BF IDT, 70V3319S133BF Datasheet - Page 12

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70V3319S133BF

Manufacturer Part Number
70V3319S133BF
Description
SRAM 256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM
Manufacturer
IDT
Datasheet

Specifications of 70V3319S133BF

Part # Aliases
IDT70V3319S133BF
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE
NOTES:
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = V
3. The output is disabled (High-Impedance state) by CE
4. Addresses do not have to be accessed sequentially since ADS = V
5. If UB, LB was HIGH, then the appropriate Byte of DATA
6. "x" denotes Left or Right port. The diagram is with respect to that port.
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Truth Table 1.
are for reference use only.
ADDRESS
DATA
UB, LB
ADDRESS
DATA
CLK
R/
CE
IL
CE
OUT
OE
, CNTEN and REPEAT = V
UB, LB
W
0
1
(4)
CLK
R/
(1)
CE
CE
OUT
OE
W
'X'
"X"
0
1
(4)
(1)
= V
= V
t
t
t
t
SW
SC
SA
SB
An
IH
t
t
t
t
SC
SW
SB
SA
t
t
t
t
IL
HC
HB
HW
An
HA
)
(1 Latency)
(2)
)
t
t
CH2
t
t
t
HW
(2,6)
HC
HB
HA
IH
t
.
CH1
t
CKLZ
t
CYC2
t
t
CD1
CKLZ
t
CYC1
t
CL2
0
(1)
An + 1
t
= V
CL1
OUT
IH
An + 1
, CE
for Qn + 2 would be disabled (High-Impedance state).
1
t
CD2
Qn
= V
t
IL
DC
IL
constantly loads the address on the rising edge of the CLK; numbers
, UB, LB = V
6.42
12
IH
t
An + 2
SB
(5)
Qn
following the next rising edge of the clock. Refer to
An + 2
t
HB
t
DC
Qn + 1
t
OHZ
Industrial and Commercial Temperature Ranges
Qn + 1
t
OHZ
t
t
OE
OLZ
t
An + 3
SC
(3)
t
t
An + 3
SC
SB
t
(3)
HC
Qn + 2
t
t
HC
HB
t
t
OE
t
OLZ
DC
(5)
t
CKHZ
Qn + 2
5623 drw 06
5623 drw 07
(5)

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