MT48H4M16LFB4-75 IT:H TR Micron Technology Inc, MT48H4M16LFB4-75 IT:H TR Datasheet

Page 1

Mobile SDRAM MT48H4M16LF – 1 Meg banks Features • 1.70–1.95V • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal ...

Page 2

Table of Contents Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

List of Figures Figure 1: 54-Ball VFBGA Ball Assignment (Top View ...

Page 4

List of Tables Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

... Figure 2: Part Numbering Diagram Example Part Number: MT48H4M16LFB4 MT48 1.8V/1.8V 54-ball VFBGA (8mm x 8mm) ”green” General Description The Micron containing 67,108,864 bits internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’ ...

Page 6

... A0-A11, ADDRESS 14 BA0, BA1 REGISTER PDF: 09005aef8237ed98/Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/ BANK0 ROW- 12 ADDRESS ROW- ADDRESS MUX MEMORY 4096 LATCH & (4,096 x 256 x 16) DECODER SENSE AMPLIFIERS I/O GATING 2 DQM MASK LOGIC BANK READ DATA LATCH CONTROL WRITE DRIVERS LOGIC ...

Page 7

... A0–A11) and READ/WRITE command (column-address A0–A7; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1. The address inputs also provide the op-code during a LOAD MODE REGISTER command ...

Page 8

Functional Description The 64Mb SDRAM (1 Meg banks quad-bank DRAM that operates at 1.8V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of ...

Page 9

The mode register must be loaded when all banks are idle, and the controller must wait t MRD before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Figure 4: Mode Register Definition BA1 BA0 ...

Page 10

A1–A7 when A2–A7 when and by A3–A7 when The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Burst Type Accesses within ...

Page 11

Figure 5: CAS Latency CLK Command DQ CLK Command DQ Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combi- nations of values for M7 and M8 are reserved for future use. ...

Page 12

... Partial-Array Self Refresh For further power savings during SELF REFRESH, the PASR feature enables the controller to select the amount of memory that will be refreshed during SELF REFRESH. The following refresh options are available: • All banks (banks and 3) • ...

Page 13

Driver Strength Bits E5 and E6 of the extended mode register can be used to select the driver strength of the DQ outputs. This value should be set according to the application’s requirements. Full-drive strength is suitable to drive higher ...

Page 14

Commands Table 5 provides a quick reference of available commands. This is followed by a written description of each command. Three additional truth tables appear following “Opera- tions” on page 18; these tables provide current state/next state information. Table 5: ...

Page 15

... DQM input logic level appearing coincident with the data given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. ...

Page 16

PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time ( whether one or all ...

Page 17

... Deep Power-Down Deep power-down is an operating mode used to achieve maximum power reduction by eliminating the power to the memory array. Data is not retained after the device enters deep power-down mode. This mode is entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# held HIGH at the rising edge of the clock, while CKE is LOW ...

Page 18

Operations Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the ...

Page 19

Figure 8: Meeting RCD (MIN) when 2 < CLK Command READs READ bursts are initiated with a READ command, as shown in Figure 8. The starting column and bank addresses are provided with the READ command, and auto precharge ...

Page 20

Figure 9: READ Command CLK CKE CS# RAS# CAS# WE# Address A10 BA0, BA1 Figure 10: Consecutive READ Bursts CLK Command Address DQ CLK Command Address DQ Note: Each READ command may be issued to any bank. DQM is LOW. ...

Page 21

Figure 11: Random READ Accesses CLK Command Address CLK Command Address Note: Each READ command may be issued to any bank. DQM is LOW. The DQM input is used to avoid I/O contention, as shown in Figure 12 on page ...

Page 22

In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvan- tage ...

Page 23

Figure 14: READ-to-PRECHARGE CLK Command Address DQ CLK Command Address DQ Note: DQM is LOW. Figure 15: Terminating a READ Burst CLK Command Address DQ CLK Command Address DQ Note: DQM is LOW. PDF: 09005aef8237ed98/Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. ...

Page 24

Fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, ...

Page 25

WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 19 on page 26, or each subsequent WRITE may be performed to a different bank. Figure 17: WRITE Burst CLK ...

Page 26

Following the PRECHARGE command, a subsequent command to the same bank cannot be issued t until In the case of a fixed-length burst being ...

Page 27

Figure 21: WRITE-to-PRECHARGE CLK ≥ 15ns DQM Command Address CLK < 15ns DQM Command Address Note: DQM could remain LOW in this example if the WRITE burst is a fixed length of ...

Page 28

PRECHARGE The PRECHARGE command (see Figure 23 on page 28) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified ...

Page 29

... Deep Power-Down Deep power-down mode is a maximum power savings feature achieved by shutting off the power to the entire memory array of the device. Data on the memory array will not be retained after deep power-down mode is executed. Deep power-down mode is entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH at the rising edge of the clock, while CKE is LOW ...

Page 30

Figure 25: Clock Suspend During WRITE Burst CLK CKE Internal Clock Command Address Note: For this example greater, and DM is LOW. Figure 26: Clock Suspend During READ Burst CLK CKE Internal Clock Command Address DQ ...

Page 31

Burst Read/Single Write The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column ...

Page 32

Figure 28: READ with Auto Precharge Interrupted by a WRITE Internal States Note: DQM is HIGH prevent D WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): When a READ to bank ...

Page 33

Figure 29: WRITE with Auto Precharge Interrupted by a READ Internal States Note: DQM is LOW. Figure 30: WRITE with Auto Precharge Interrupted by a WRITE Internal States Note: DQM is LOW. PDF: 09005aef8237ed98/Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C ...

Page 34

Table 6: Truth Table 2 – CKE Notes: 1–4; notes appear below table CKE CKE Current State Power-down Self refresh Clock suspend Deep power-down L H Power-down Deep power-down Self refresh Clock suspend H ...

Page 35

Table 7: Truth Table 3 – Current State Bank n, Command to Bank n Notes: 1–5; notes appear below table and on next page Current State CS# RAS# CAS# Any Idle ...

Page 36

The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Accessing mode register: Precharging all: 5. All states and sequences not ...

Page 37

Table 8: Truth Table 4 – Current State Bank n, Command to Bank m Notes: 1–6; notes appear below table and on next page Current State CS# RAS# Any Idle X X Row L L activating, ...

Page 38

A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m ...

Page 39

Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of ...

Page 40

Table 12: Electrical Characteristics and Recommended AC Operating Conditions Notes and 11; notes appear on page 43 and 44 AC Characteristics Parameter Access time from CLK (positive edge) Address hold time Address setup time CLK high-level ...

Page 41

Table 13: AC Functional Characteristics Notes and 11; notes appear on page 43 and 44 Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit ...

Page 42

Table 15 Self Refresh Current Options DD Notes: 4, 13, 25, and 28; notes appear on page 43 and 44; V Temperature-Compensated Self Refresh Parameter/Condition Self refresh current: CKE < 0.2V – 4 banks open Self refresh ...

Page 43

Notes 1. All voltages referenced This parameter is sampled. V 1.4V MHz with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications ...

Page 44

The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including used to reduce the data rate. 24. For auto ...

Page 45

Timing Diagrams Figure 32: Initialize and Load Mode Register CLK ( ( ) ) CKS CKH ( ( ) ) CKE ( ( ) ) t t CMS CMH ( ( ...

Page 46

Figure 33: Power-Down Mode CLK CKE t CKS t CKH t CMS t CMH Command PRECHARGE DQM A0–A9, A11 All banks A10 Single bank BA0, BA1 Banks\S) High-Z DQ Two clock cycles ...

Page 47

Figure 34: Clock Suspend Mode CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH Command READ NOP t CMS t CMH DQM A0–A9, A11 ...

Page 48

Figure 35: Auto Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH Command PRECHARGE DQM A0–A9, A11 All banks A10 Single bank BA0, BA1 Bank(S) High-Z DQ Precharge all active ...

Page 49

Figure 36: Self Refresh Mode T0 T1 CLK CKE t CKS t CKH t CMS t CMH Command PRECHARGE NOP DQM A0–A9, A11 All Banks A10 Single Bank BA0, BA1 Bank(s) High-Z ...

Page 50

Figure 37: READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM A0–A9, A11 Row ...

Page 51

Figure 38: READ – with Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM A0–A9, A11 Row Enable auto precharge Row ...

Page 52

Figure 39: Single READ – Without Auto Precharge CLK t CKH t CKS CKE t CMS t CMH Command ACTIVE NOP t CMS DQM A0–A9, A11 Row ...

Page 53

Figure 40: Single READ – with Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM A0–A9, A11 Row A10 Row t ...

Page 54

Figure 41: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM A0–A9, A11 Row Enable auto precharge A10 Row ...

Page 55

Figure 42: READ – DQM Operation CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM A0–A9, A11 Row Enable auto precharge Row A10 ...

Page 56

Figure 43: WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP WRITE t CMS DQM Column m 3 A0–A9, A11 ...

Page 57

Figure 44: WRITE – with Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Column m 2 A0–A9, A11 Row t ...

Page 58

Figure 45: Single WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM A0–A9, A11 Row A10 ...

Page 59

Figure 46: Single WRITE – with Auto Precharge CLK t CKS t CKH CKE t CMS t CMH NOP 4 NOP 4 Command ACTIVE DQM A0–A9, A11 Row t ...

Page 60

Figure 47: Alternating Bank Write Accesses CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Column m 2 A0–A9, A11 Row t AS ...

Page 61

Figure 48: WRITE – DQM Operation CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM A0–A9, A11 Row Row A10 ...

Page 62

Package Dimensions Figure 49: 54-Ball VFBGA (8mm x 8mm) 0.65 ±0.05 Seating plane C 0.10 C 54X Ø0.45 ±0.05 Solder ball diameter refers to post-reflow condition. The pre-reflow diameter is 0.42. Ball A9 6.40 3.20 ±0.05 3.20 ±0.05 8.00 ±0.10 ...