IS61LV12816L-10TL ISSI, Integrated Silicon Solution Inc, IS61LV12816L-10TL Datasheet - Page 11
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IS61LV12816L-10TL
Manufacturer Part Number
IS61LV12816L-10TL
Description
IC SRAM 2MBIT 10NS 44TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
Asynchronousr
Datasheet
1.IS61LV12816L-10TL.pdf
(16 pages)
Specifications of IS61LV12816L-10TL
Memory Size
2M (128K x 16)
Package / Case
44-TSOP II
Interface
Parallel
Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Speed
10ns
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Access Time
10 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3.135 V
Maximum Operating Current
60 mA
Organization
128 K x 16
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
- 0.5 V to + 4 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
706-1033
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Manufacturer
Quantity
Price
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IS61LV12816L
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. F
10/27/05
WRITE CYCLE NO. 4
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t
referenced to the rising or falling edge of the signal that terminates the Write.
ADDRESS
UB, LB
D
OUT
WE
D
OE
CE
IN
LOW
DATA UNDEFINED
(LB, UB Controlled, Back-to-Back Write)
t
HZWE
ADDRESS 1
t
SD
t
t
WORD 1
SA
WC
t
PBW
HIGH-Z
DATA
VALID
IN
1-800-379-4774
t
t
HD
HA
t
SA
ADDRESS 2
t
t
(1,3)
SD
WC
WORD 2
t
PBW
DATA
VALID
IN
t
LZWE
SA
t
HD
t
, t
HA
HA
, t
SD
, and t
UB_CEWR4.eps
HD
ISSI
timing is
11
®