IS61LV12816L-10TL ISSI, Integrated Silicon Solution Inc, IS61LV12816L-10TL Datasheet - Page 8
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IS61LV12816L-10TL
Manufacturer Part Number
IS61LV12816L-10TL
Description
IC SRAM 2MBIT 10NS 44TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
Asynchronousr
Datasheet
1.IS61LV12816L-10TL.pdf
(16 pages)
Specifications of IS61LV12816L-10TL
Memory Size
2M (128K x 16)
Package / Case
44-TSOP II
Interface
Parallel
Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Speed
10ns
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Access Time
10 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3.135 V
Maximum Operating Current
60 mA
Organization
128 K x 16
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
- 0.5 V to + 4 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
706-1033
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS61LV12816L-10TL
Manufacturer:
ISSI
Quantity:
1 000
Company:
Part Number:
IS61LV12816L-10TL
Manufacturer:
ISSI
Quantity:
153
Part Number:
IS61LV12816L-10TL
Manufacturer:
ISSI
Quantity:
20 000
Company:
Part Number:
IS61LV12816L-10TL-TR
Manufacturer:
ISSI
Quantity:
1 000
Part Number:
IS61LV12816L-10TL-TR
Manufacturer:
ISSI
Quantity:
20 000
Company:
Part Number:
IS61LV12816L-10TLI
Manufacturer:
ISSI
Quantity:
5 510
Part Number:
IS61LV12816L-10TLI
Manufacturer:
ISSI
Quantity:
20 000
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
IS61LV12816L
8
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
WC
SCE
AW
HA
SA
SD
HD
HZWE
LZWE
PBW
PWE
PWE
3.0V and output loading specified in Figure 1.
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write.
1
2
(3)
(3)
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
Integrated Silicon Solution, Inc. — www.issi.com —
Min.
6.5
6.5
—
8
7
7
0
0
6
4
0
0
-8 ns
Max
—
—
—
—
—
—
—
—
—
—
—
3
(1,3)
Min. Max.
10
—
8
8
0
0
7
8
5
0
0
8
-10 ns
(Over Operating Range)
—
—
—
—
—
—
—
—
—
—
—
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ISSI
1-800-379-4774
10/27/05
Rev. F
®