IS42S16800D-7TL ISSI, Integrated Silicon Solution Inc, IS42S16800D-7TL Datasheet - Page 47
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IS42S16800D-7TL
Manufacturer Part Number
IS42S16800D-7TL
Description
IC SDRAM 128MBIT 143MHZ 54TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet
1.IS42S16800D-7TL.pdf
(62 pages)
Specifications of IS42S16800D-7TL
Package / Case
54-TSOP II
Memory Size
128M (8Mx16)
Format - Memory
RAM
Memory Type
SDRAM
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Data Bus Width
16 bit
Maximum Clock Frequency
143 MHz
Access Time
6.5 ns, 5.4 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
130 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
706-1020
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IS42S81600D,
PRECHARGE
The PRECHARGE command (see figure) is used to deac-
tivate the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent row
access some specified time (t
command is issued. Input A10 determines whether one or
all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. When all banks are to be precharged, inputs BA0,
BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated prior
to any READ or WRITE commands being issued to that
bank.
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident
with a NOP or COMMAND INHIBIT when no accesses are
in progress. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power-
down occurs when there is a row active in either bank, this
mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding
CKE, for maximum power savings while in standby. The
device may not remain in the power-down state longer than
the refresh period (64ms) since no refresh operations are
performed in this mode.
The power-down state is exited by registering a NOP or
COMMAND INHIBIT and CKE HIGH at the desired clock
edge (meeting t
POWER-DOWN
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
CKS
). See figure below.
COMMAND
IS42S16800D
CKE
CLK
All banks idle
Enter power-down mode
RP
) after the PRECHARGE
t
NOP
CKS
Input buffers gated off
less than 64ms
PRECHARGE Command
Exit power-down mode
BA0, BA1
A0-A9, A11
CKE
RAS
CAS
CLK
A10
WE
CS
t
CKS
HIGH
NOP
DON'T CARE
BANK ADDRESS
BANK SELECT
ACTIVE
ALL BANKS
t
t
t
RCD
RAS
RC
47