IS42S16800D-7TL ISSI, Integrated Silicon Solution Inc, IS42S16800D-7TL Datasheet - Page 49
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IS42S16800D-7TL
Manufacturer Part Number
IS42S16800D-7TL
Description
IC SDRAM 128MBIT 143MHZ 54TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet
1.IS42S16800D-7TL.pdf
(62 pages)
Specifications of IS42S16800D-7TL
Package / Case
54-TSOP II
Memory Size
128M (8Mx16)
Format - Memory
RAM
Memory Type
SDRAM
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Data Bus Width
16 bit
Maximum Clock Frequency
143 MHz
Access Time
6.5 ns, 5.4 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
130 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
706-1020
Available stocks
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Price
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Quantity:
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IS42S81600D,
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming
the write burst mode bit (M9) in the mode register to a logic 1.
In this mode, all WRITE commands result in the access of a
single column location (burst of one), regardless of the
programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9 = 0).
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another bank
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supports CONCURRENT AUTO PRECHARGE. ISSI
SDRAMs support CONCURRENT AUTO PRECHARGE.
READ With Auto Precharge interrupted by a READ
READ With Auto Precharge interrupted by a WRITE
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
COMMAND
Internal States
COMMAND
Internal States
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
DQM
CLK
CLK
DQ
DQ
IS42S16800D
READ - AP
BANK n,
Page Active
BANK n
T0
T0
COL a
NOP
Page Active
CAS Latency - 3 (BANK n)
BANK n,
READ - AP
COL a
T1
BANK n
T1
NOP
Page Active
Page Active
READ with Burst of 4
READ with Burst of 4
CAS Latency - 3 (BANK n)
T2
T2
NOP
NOP
BANK n,
READ - AP
COL b
BANK m
T3
T3
NOP
D
OUT
a
CAS Latency - 3 (BANK m)
Four cases where CONCURRENT AUTO PRECHARGE
occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge):
2. Interrupted by a WRITE (with or without auto precharge):
Interrupt Burst, Precharge
A READ to bank m will interrupt a READ on bank n, CAS
latency later. The PRECHARGE to bank n will begin
when the READ to bank m is registered.
A WRITE to bank m will interrupt a READ on bank n when
registered. DQM should be used three clocks prior to the
WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to
bank m is registered.
WRITE - AP
BANK m,
BANK m
T4
T4
NOP
COL b
D
D
IN
t
OUT
RP - BANK n
READ with Burst of 4
b
a
Interrupt Burst, Precharge
WRITE with Burst of 4
T5
T5
D
NOP
NOP
D
IN
OUT
t
b+1
RP - BANK n
a+1
T6
T6
D
NOP
NOP
D
IN
OUT
b+2
b
DON'T CARE
DON'T CARE
Idle
T7
T7
D
NOP
NOP
D
Write-Back
IN
Precharge
OUT
b+3
t
t
RP - BANK m
DPL - BANK m
b+1
Idle
49