IS42S32800B-7BL ISSI, Integrated Silicon Solution Inc, IS42S32800B-7BL Datasheet - Page 11
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IS42S32800B-7BL
Manufacturer Part Number
IS42S32800B-7BL
Description
IC SDRAM 256MBIT 143MHZ 90BGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS42S32800B-7BL.pdf
(62 pages)
Specifications of IS42S32800B-7BL
Package / Case
90-BGA
Memory Size
256M (8Mx32)
Format - Memory
RAM
Memory Type
SDRAM
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Data Bus Width
32 bit
Organization
2 Mbit x 32
Maximum Clock Frequency
143 MHz
Access Time
7 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
150 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Density
256Mb
Address Bus
14b
Access Time (max)
5.5ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
BGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
150mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
706-1024
Available stocks
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Price
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IS42S32800B-7BL
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ISSI, Integrated Silicon Solution Inc
Quantity:
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I
5
IS42S32800B
Integrated Silicon Solution, Inc.
Rev. F
07/21/09
CLK
COMMAND
DQ0 - DQ3
CLK
ADDRESS
COMMAND
CAS# latency=2
t CK2 , DQ s
CAS# latency=3
t CK3 , DQ s
A write burst without the AutoPrecharge function may be interrupted by a subsequent Write, BankPrecharge/
PrechargeAll,or Read command before the end of the burst length.An interrupt coming from Write command can
occur on any clock cycle following the previous Write command (refer to the following figure).
Write command
(RAS#=”H”,CAS#=”L”,WE#=”L”,BS =Bank,A10 =”L”,A0-A8 =Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active
bank.The bank must be active for at least tRCD(min.)before the Write command is issued.During write bursts,
the first valid data-in element will be registered coincident with the Write command.Subsequent data elements
will be registered on each successive positive clock edge (refer to the following figure).The DQs remain with high-
impedance at the end of the burst unless another command is initiated.The burst length and burst sequence are
determined by the mode register,which is already programmed.A full-page burst will continue until terminated (at
the end of the page it will wrap to column 0 and continue).
Burst Write Operation (Burst Length =4,CAS#Latency =2,3)
The first data element and the write
are registered on the same clock edge.
READ A
Col A
Bank,
T0
T0
NOP
WRITEA
DIN A 0
Read to Precharge (CAS#Latency =2,3)
T1
T1
NOP
I
DOUT A 0
DIN A 1
T2
T2
NOP
NOP
DOUT A 0
DIN A 2
T3
T3
NOP
DOUT A 1
NOP
Bank(s )
Precharge
DOUT A 2
DIN A 3
T4
T4
NOP
DOUT A 1
Extra data is masked.
don’t care
DOUT A 2
T5
T5
DOUT A 3
NOP
NOP
t
RP
T6
T6
DOUT A 3
NOP
NOP
Activate
T7
Bank,
Row
T7
NOP
I
T8
T8
NOP
NOP
®
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