IS42S32160C-6BI ISSI, Integrated Silicon Solution Inc, IS42S32160C-6BI Datasheet - Page 11
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IS42S32160C-6BI
Manufacturer Part Number
IS42S32160C-6BI
Description
IC SDRAM 512MB 166MHZ 3.3V 90BGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet
1.IS42S32160C-6BI.pdf
(60 pages)
Specifications of IS42S32160C-6BI
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (16M x 32)
Speed
166MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
90-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
Q5246106
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S32160C-6BI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
IS42S32160C
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
01/22/09
CLK
COMMAND
DQ’s
CLK
COMMAND
CAS# latency=2
t CK2 , DQ’s
Note:The DQMs can remain low in this example if the length of the write burst is 1 or 2.
CAS# latency=3
t CK3 , DQ’s
CLK
DQM
COMMAND
ADDRESS
DQ
The Read command that interrupts a write burst without auto precharge function should be issued one cycle after
the clock edge in which the last data-in element is registered. In order to avoid data contention, input data must
be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to Figure
"Write Interrupted by a Read". Once the Read command is registered, the data inputs will be ignored and writes
will not be executed.
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function
should be issued m cycles after the clock edge in which the last data-in element is registered,where m equals tWR/
tCK rounded up to the next whole number. In addition, the DQM signals must be used to mask input data, starting
with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/
PrechargeAll command is entered (refer to the Figure "Write to Precharge").
: don't care
Write Interrupted by a Write (Burst Length =4, CAS# Latency =2,3)
Write Interrupted by a Read (Burst Length =4, CAS# Latency =2,3)
T0
T0
NOP
NOP
BANK
COL n
WRITE
DIN
T0
n
Input data for the write is masked.
WRITEA
WRITEA
DIN A 0
T 1
T1
DIN A 0
DIN A 0
1 Clk Interval
DIN
NOP
n + 1
T1
t WR
WRITEB
READ B
DIN B 0
don’t care
don’t care
T2
T2
Precharge
BANK (S)
T2
Write to Precharge
DIN B 1
don’t care
T3
T3
NOP
NOP
NOP
DI N
T3
DIN B 2
T4
NOP
T4
NOP
t RP
DOUT B 0
NOP
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
T4
DIN B 3
T5
T5
NOP
NOP
DOUT B 0
DOUT B 1
Activate
ROW
T5
T6
NOP
T6
NOP
DOUT B 2
DOUT B 1
NOP
T6
T7
NOP
T7
DOUT B 3
NOP
DOUT B 2
T8
NOP
T8
NOP
DOUT B 3
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